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TAS5713: DRC register sizes, PBTL, and clock autodetection

steve polychronopolis
Prodigy 60 points
Part Number: TAS5713
Other Parts Discussed in Thread: TAS5733L,

A few questions I'd like to be sure of...

1.  The datasheet specifies registers 40 and 43 as 8 bytes.  However, the GUI tool generates 4-byte values for these locations.  I'm unsure why it generates any, as we're not using DRC.  Which is correct?

2.  We're using PBTL mode with A, B driving one side and C, D driving the other.  The datasheet suggests programming 0x25 (PWM mux) to 0x01, 0x10, 0x32, 0x45.  For a mono application using channel 1, for instance, it seems more likely that 0x01, 0x00, 0x22, 0x45 would be more effective.  Are we misinterpreting the usage of this register?

3.  I'm not entirely clear on rate detection and bank switching...

    a) Bank switching appears to be disabled by default.  Should it or must it be enabled for proper rate detection, or does it just choose biquad coefficients?  I'm not sure how to map the biquads to the banks, and the inclusion of 3a-3f seems odd since this includes some but not all of the DRC registers and a reserved location.

    b) Register 0 is described as a status register, but the GUI appears to write to it.  Does it need to be written under any circumstances?

  • 0
    TI__Expert 6985 points
    Hello Steve! Shawn will help you with your questions, but have you also looked at our newer devices in this family to include the TAS5733L or TAS5751/3? These also devices use newer tools such as the PurePath Console 3 GUI tool and are much easier to apply. Thanks, Jeff
  • 0
    TI__Mastermind 24835 points

    Hi Steve,

    My ansewers are as below:

    1. I'm sorry that this is a software issue, please follow the description in the datasheet.

    2. In PBTL mode, all four channels(8 MOSFET) are used to drive the load/speaker. In this mode, a lower resistance speaker can be used and a higher output current/power can be achieved. Then if only use two channels(by setting 0x01, 0x00, 0x22, 0x45 in register 0x25), it actually works in BTL mode. So please set 0x01, 0x10, 0x32, 0x45 in the register 0x25 for PBTL mode.

    3. You are right, this is a typo in datasheet. It should be '0x3B-0x40'. Not all of DRC registers are used in auto detection. 

    4. For the clock control register, it is read only with clock auto detect enabled.

    Best regards,

    Shawn Zheng

  • 0 in reply to Shawn Zheng
    Prodigy 60 points

    I'm still confused about your PBTL advice.  I'm using a single channel and just want to parallel the drivers.  It seems the recommendation drives each connected pair, which are shorted to each other, with different outputs, while it seems that if the outputs are shorted, they should be driven by the same signal or they'll potentially conflict and create shorts from power to ground.  The configuration 0x10, 0x32 connects PWM channels 2 and 1 to outputs A and B respectively, and the two outputs are shorted together.  The same happens with the inverted outputs on C and D.  Is it assumed that the channels are configured to exactly the same input mix and gain, and so they drive the PWM outputs identically?

    Maybe I'm not understanding register 0x25, or maybe I'm unclear on how PBTL differs from mono BTL.  Please help me understand.

    Also, you mention having clock auto detect enabled.  I'm not finding a register that enables or disables it.  Is it enabled by enabling bank switching, or is that something different?  And should I use the factory oscillator trim?

  • 0 in reply to steve polychronopolis
    TI__Mastermind 24835 points

    Hi Steve,

    About PBTL mode, I think I misunderstood your question, very sorry. If you set the resgister 0x25 with 0x01 0x00 0x22 0x45, PBTL mode still works functionally. But this processing path is not optimized, so I'm not sure the stability/reliability/performance for this configuration. So please set the reg0x25 with 0x01, 0x10, 0x32, 0x45, which is the TI's recommendation. And please also set reg0x19 with 0x3A. One thing need to be noted is that, please connect the OUTA and OUTB(or OUTC and OUTD) after the LC filter instead of on the pins directly, which means that you still need 4 inductors in PBTL application.

    The band switching control bits are in register 0x50. Please refer to more details in section BANK SWITCHING in page34 in TAS5713 datasheet.

    OSC trim has to be done during initialization by writing 0x00 to register 0x1B. Please follow the procedure in section Initialization Sequence in Page37 in TAS5713 datasheet.

    Best regards,

    Shawn Zheng

     

     

  • 0 in reply to Shawn Zheng
    TI__Mastermind 24835 points
    Hi Steve,
    To make the things clear, please see the following configuration for PBTL mode:
    1. 4 OUTPUT are used. Set register 0x19 with 0x30 to enable all 4 PWM outputs. Set register 0x25 with 0x01 10 32 45. In this configuration, connect OUTA with OUTB and OUTC with OUTD after LC filter. Your configuration is to set register 0x19 with 0x3A and set register 0x25 with 0x01 00 22 45. It also works functinally, but I'm not sure the reliability/stability.
    2. 2 OUTPUT are used. Set register 0x19 with 0x3A and set register 0x25 with 0x01 10 32 45. In this mode, only OUTB and OUTD are switching.
    Best regards,
    Shawn Zheng
  • 0 in reply to Shawn Zheng
    TI__Expert 6985 points
    Hi Steve! Did this answer your question and if so, can we close this thread? Thanks, Jeff