TLV320AIC3101: criteria in case fs chage

Hi, Shibatani-san,

The sequence written by customer is correct, however, I cannot see if the dual rate for ADC and DAC is configured. ADC and DAC dual rate is configured in register 7, could you please check with customer when is this register configured. In general, the sequence is correct, before changing any sampling rate in the device, the ADC/DAC should be turned Off to void any possible noise artifacts. One thing to note with this type of applications is that when using the PLL, the coefficients should be updated only when disabling first the PLL. Could you provide more details about the issue customer is experiencing?.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Dear Melendez-san

Thank you for your reply, and I am sorry the delay of my reply because

I had talked with my customer face to face again.

Here is information from customer ===== following.

Please allow me to have Customer had additinal question.

Q1   I add "wait time"  between PLL disable and PLL setting  for next firmware , but is it no problem?  I think so  " .. see attached

Q2   If there were any criteria to be kept for PLL disable~ PLL setting, please advise.

======================

Information-1

Where Dual rate ( Page0 Reg7 has set) is in following.

I think there are no problem, but please have your opinion.

DAC/ADC mute,then power down

Set I2S slave ( -- do this, otherwise, PLL could n't be disable)

Set PLL disable

Set Dual rate

Set P,R,J, D

SetI2S Master

Set PLL Enable

wait 11ms

ADC/DAC power up then unmute

information 2  What is Customer's Problem detail

When customer change fs from 48kHz to 96KHz ( TLV320AIC3101 is I2S master),

change C55x DSP sys clock from 75MHz to 120MHz.

Audio processing algorithm on C55x works depend on input fs from AIC3101.

If WCLK, BCLK became from 48KHz to 96KHz,

and DSP sys clock is still 75MHz, then DSP processing collapses  and system stucks.

So customer set WCLK / BCLK to be stopped to wait DSP sys clock comes up correctly.

In the previous model if customer, DSP sys clock was same, so there were no problem  .

=================

Thank you for your support again.

Best Regards

flow of fs_change for AIC3101_PLL disable.pptx

Hi, Shibatani-san,

Thanks for the feedback. There is no problem in adding a delay time between PLL disable while waiting for the DSP to receive a different clock. The sequence followed by customer seems good, So I think there should be no issues.

Best Regards,

  -Diego Meléndez López
   Audio Applications Engineer

Dear Melendez san

Thank you for your answer so quickly.

I'll inform your answer to customer .

Thank you again

Dear Melendez san

I am sorry to bother you again.

Please let me ask again due to customer's inquiry.

Q1

Is there any " Don'ts "  in the waiting between PLL disable and PLL setting  in order to keep WCLK/BCK stopped ?

( I think so,  I think nothing prohibited except software reset :Page0 Reg1. .... If I set P0R8=80, I should set all from initial state )

Q2

When I check i2c log in EVM and ,setting  PLL disable, i2c log is following.~~~~

Do you recommend if I PLL disable in the GUI , GUI send not only Page0 Rge3 jonly, but also  Page0 Reg 4~6 and Reg 11 ?

Is this  recommended? 

I intend to recommend customer  as EVM does, but why ?? 

~~~~~

>w 30 03 11 20 00 00

>w 30 0B 01

~~~~

Best Regards

flow of fs_change for AIC3101_PLL disable_Again.pptx

Dear Melendez san

Thank you for your quick answer.

Customer understood for your answer.

Please close this

Thank you again