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TLV320AIC10: Audio forum

Mochi
Genius 3915 points
Part Number: TLV320AIC10
Other Parts Discussed in Thread: TLV320AIC3100

Hello,
Our customer is facing issue of little bit older device that TLV320AIC10.
In Master mode, AIC10 generate SCLK and FS clocks. However those output clocks will violated DAC Data input  setup time requirement itself.

Here is the mode setting and input MCLK frequency.
M1=1 M0=1 M/S=1 Frame-Sync (FS) Function—Master Mode
Register1=0x04(decimation/FIR Bypass)
Register2=0x06(N=6)
Register3=0x01(16-bit data format)
Register4=0x00(DAC PGA gain=0dB)
MCLK=19.6608MHz

Captured waveform are followings.
Because of this FS-SCLK timing violation our DSP cannot catch appropriate 1st SCLK falling edge to output 16bit MSB data to DAC and violate tsu requirement.

 

Q1:It seems SCLK clock is 4bit block busted output, it is unusual SCLK format, normally Audio converter SCLK output is continues clock. Is it correct function of AIC10 internal clock divider ?

Q2: Is there any good solution to keep Setup time tSU 5nsec(mini) requirement for DAC Data input when we use this very narrow FS falling edge to SCLK falling edge clock timings from master mode AIC10 generated?

Regards,
Mochizuki

  • 0
    TI__Mastermind 30080 points

    Mochizuki-san,

    I will do my best to help you,  but I must tell you that this is a legacy device, and the design files are archived and design support is extremely limited.

    I notice that that the datasheet mentions SCLK in a note under control register 2.

    I looks like you have the FIR bypassed and N= 6. Is it possible you could change N to 4 or 8?  and see what happens?

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    Genius 3915 points

    Hi Steve-san,

    Thank you for your support.

     

    We have changed N setting at MCLK=24.576MHz, below is captured waveform at N=3.

    Now, SCLK is continuous and Tsu is more than 5nsec. It seems appropriate Master clock output.

     

    In this project Fs is 12KHz range, then we tried workaround clock setting as MCLK=9.83MHz N=3 Fs=12.8Kz.

    It is also enough Tsu margin. Do you see N=6 is not recommended setting and suggest the customer to use N=3?

     

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    TI__Mastermind 30080 points
    Mochizuki-san,

    is there a reason the customer cannot use an even N value?

    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Genius 3915 points

    Hi Steve-san,

    When look at following Note, N=3 is suggested number to get 50% duty SCLK at cascade=1 configuration.

    Is it better to use Even number setting?

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    TI__Mastermind 30080 points
    Mochizuki-san,

    That note specifically says that the device will not produce a 50% duty cycle SCLK when:
    Cascade is less than or equal to 4, FIR is bypassed and N is NOT 4, 8, 12, 16, 20,24, 28 or 32.

    In your case, cascade is 1, your FIR is bypassed and N is NOT 4, 8, 12, 16, 20 ,24, 28 or 32.

    As I've said before this is a legacy device and I do not have full resources available to support it. I can't say that this will fix the problem, but It does appear that your configuration is not recommended.

    -Steve
  • 0 in reply to Steve-Wilson
    Genius 3915 points

    Steve-san,

    We understood the situation.

    Our customer wants to confirm followings.

     

    1. Their workaround setting N=3 is not prohibited number. Is this correct?

    2. Additional question is coming up about "Th" DIN hold time 1/2T+5nsec(MIN) specification.

    If SCLK duty is not 50% like previous waveform, SCLK L edge is not related 1/2T point.

    Newer CODEC TLV320AIC3100's "Th" requirement is referring SCLK L edge timing, it is more realistic specification.

    Can we expect to internal function should be same?

     

    Regards,

    Mochizuki

  • 0 in reply to Mochi
    TI__Mastermind 30080 points
    Mochizuki,

    1. I don't see anything in the datasheet that says it is prohibited, only that it will not create the produce a 50% duty cycle SCLK.

    2. This is an issue I will not be able to provide an adequate answer on. As mentioned before, this device is legacy, the design files are archived, and there are no current design engineers at TI who worked on this device. This product remains active for customers currently using it, for practical purposes it is NRND

    best regards,
    -Steve Wilson
  • 0 in reply to Steve-Wilson
    Genius 3915 points

    Steve-san,

    Thank you for your reply, I understand the situation.

    Let's close this sled.

    Regards,

    Mochizuki