Initializing and debugging TAS3204

Good morning Drew,

thank you for your fast reply to my problem. It's good to hear that the TAS streams Audio through the analog ports in the I/O test configuration. That makes testing the board a lot easier. At the moment I'am using my system controller to controll the DSP with a sequence like this: powering board -> reset pin held low -> setting GPIO1 pin low -> powering dsp -> wait 20ms -> releasing reset.

Regarding the VMID voltage you just confirmed my suspicion that it's level should be around 1.6V. Unfortunately the board lies in the lab of my university and now it is a weekend so I can't check the VMID connection till monday. In the meantime I did what I could and tripple checked my circuit diagram and found something interesting. In this datasheet for the TAS3204

http://focus.ti.com/lit/ds/symlink/tas3204.pdf

in section 2.3 terminal descriptions you are directed to decouple the VMID pin with a 100nF and a 10uF ceramic cap furthermore the VREF pin is only decoupled with a single 100nF capacitator. Now if we jump to the application information scematics in section 14.1 we see that all the reference voltage pins are decoupled via identical 100nF and 4.7uF capaciator networks. So now I'am a little bit confused. I don't expect the 10uF cap on the VMID pin to be a problem in comparison to a 4.7uF cap. What bugs me is the single 100nF cap at the VREF pin. If there is missing a filter cap it could be another problem. So it would be nice if you could check this for me until I can make measurements on my board on monday.

best regards,

Christopher

Christopher K. said:

I don't expect the 10uF cap on the VMID pin to be a problem in comparison to a 4.7uF cap.

  This isn't a problem,  whether its a 4.7uF, or a 10uF cap, its there to provide bulk charge storage at the pin to keep the voltage at ~AVDD/2 under heavy loads.

Christopher K. said:

hat bugs me is the single 100nF cap at the VREF pin.

This is just a power supply decoupling cap. Standard practice in industry to mitigate real world noise that is coupled on the internal voltage regulators output. If you don't have a bulk cap on the VREF pin, it's value should still be at AVDD/2 since the voltage is generated internally.

For verification purposes, you can simply swap the 4.7uF caps with 10uF and observe if you find any changes. You could also stick on the 4.7uF or 10uF cap on the VREF pin and observe for any changes. This will hopefully settle your concerns.

However, from the purely theoretical standpoint, changing the value of the cap will not cause the AVDD pins to be pulled down to 200mV as caps do not pass DC. I suspect you have a board issue, -or- your TAS3204 device has suffered from Electrical Overstress due to handling without the necessary precautions. If it's the later, you should be able to get some free samples from TI.com so you can swap it out.

To clarify

VREF will be at 1.2V or so I believe.

VMID should be at ~AVDD/2

Hello Drew,

seems like I found the source of my problem. I wanted to use the VMID Voltage of the TAS3204 to reference an OPA1632 diffential amplifier. For that purpose I buffered the VMID Voltage with a seperate 4.7uF electrolyte capacitator and applied the VMID Voltage to the VCOM pin of the OPA1632. At least that was the plan, 'cause as soon as I make the connection between the DSP and the OPA the VMID Voltage drops to 300mA. Now I have to find another way, to reference my OPA to the VMID voltage of the TAS DSP or would you say, that this solution normaly should work?

best regards,

Christopher

Ok, now I'm referencing the OPA1632 via a resistor divider and the VMID Voltage is stable at 1.55V. VREF is 1.2V so far everything looks good, but still no output from the TAS. I tried switching the positiv and negativ signal on the analog input pins in case I got the polarity wrong, still no improvement.

Chris,

Christopher K. said:

For that purpose I buffered the VMID Voltage with a seperate 4.7uF electrolyte capacitator and applied the VMID Voltage to the VCOM pin of the OPA1632

I'm not sure I understand when you say you 'buffered' the VMID pin with a 4.7uF Cap. Simply adding another cap isn't really buffer, as the pin is not decoupled from your OPA circuit. Keep in mind that the VMID pin is characterized by voltage as well as current. If the VMID pin cannot supply enough current to power the OPA (which in this case is true), you'll need to rework your circuitry to overcome this issue.

Since I highly suspect this is a class project, and you are paying a good chunk of change for the learning experience, I'm not going to give you the answer of how to do this, - however - I will hint that finding a way to reference VCOM pin from TAS3204 VMID is the best solution,  as the DC offsets / mismatched references in the audio signal chain may distort the quality of  the audio (and probably decrease your grade in the class).

Best of luck in developing your debugging skills,

Hello Drew,

you're right, powering the OPA from the TAS VMID pin wasn't  a very smart idea. The workaround with a voltage divider was the quick and dirty way to get a fast solution without reworking the board layout. So as an more elegant way I'am thinking about something like a unity gain amplifier for the next version of the board. Until that, the main problem remains, the TAS won't output a single tone. Maybe I should give it a try and replace the TAS. But on the other hand, seems the TAS to be ok, all voltages are within their given limits, the xtal is running, i2c communication with the eeprom is happening and even the system contoller seems to be configured the right way, to archive the I/O test mode.

Argh I need a break,

Christopher

Chris,

      You can also try simply programming the device. The ROM bootloader will only enter test mode under certain conditions. If the EEPROM image is valid, it will never enter test mode - so simply removing the EEPROM may will eliminate some of the variables in your system.