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PCM1808-Q1: Supporting Fs=16kHz with system clock of 768fs in slave mode

Yoshikazu Kawasaki
Expert 3510 points
Part Number: PCM1808-Q1
Other Parts Discussed in Thread: PCM1808, PCM1860, PCM1803, PCM1802, PCM1804, PCM1860-Q1

Hello,

My customer was wondering how they should do for the existing system working at Fs=16kHz with system clock of 768fs in slave mode.  They'd like to use PCM1808-Q1 as it is without changing their SW, but it doesn't seem to support 768fs.  How would you say for this use case?  Do you have an IC supporting this use case?  Note that they prefer HW control.

One of the solution would be using external 1/2 divider for the system clock to make it 384fs from 12.288MHz to 6.144MHz if it doesn't support 768fs.  Do you think it works with PCM1808-Q1?  If it does, what do they have to check?  The datasheet just shows the Figure 22, but does it all they have to check for the timings?  I mean aren't there any timing requirements between SCKI and I2S pins?

3603.SlaveModeTimingRequirements.docx

Best Regards,

Yoshikazu Kawasaki

  • 0
    TI__Mastermind 23050 points

    Hi Yoshikazu,

    PCM1808 does not support a system clock of 768*fs. We actually do not have any hardware controlled devices that support a system clock that high so a divider would be necessary.

    PCM1860 can actually operate without a system clock though and derive its own master clock from the incoming BCLK and FSYNC if it is operating in slave mode. This may also be an option.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    TI__Expert 3510 points

    Hello Zak,

    PCM1808-Q1 datasheet on page 18 says "In slave mode, the PCM1808-Q1 operates under LRCK (pin 7), synchronized with system clock SCKI (pin 6). The PCM1808-Q1 does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI."

    Therefore it doesn't look the system clock(SCKI) isn't required.  Would you please let me confirm if PCM1808-Q1 really doesn't require SCKI input in slave mode?  If it doesn't, would you please tell me what "PCM1808-Q1 does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI" mean?  How can PCM1808-Q1 find the synchronization between LRCK and SCKI without SCKI?

    Best Regards,

    Yoshikazu Kawasaki

  • 0 in reply to Yoshikazu Kawasaki
    TI__Mastermind 23050 points

    Hi Kawasaki-san,

    It is PCM1860 that does not require a SCKI as we have discussed in your other post. The PCM1808 always requires an SCKI.

    Best,

    Zak

  • 0 in reply to Zak Kaye
    TI__Mastermind 23050 points

    Hi Kawasaki-san,

    I actually wanted to clarify that some of our other PCM180x devices do actually support an SCKI of 768*fs. You can look at the PCM1802, PCM1803, and PCM1804. My apologies, the PCM1808 does not support this and I thought the other devices in the family were similar in this regard but I was mistaken!

    Best,

    Zak

  • 0 in reply to Zak Kaye
    TI__Expert 3510 points

    Hello Zak,

    Thank you very much for your quick reply again.

    OK, I understand PCM1860-Q1 doesn't require SCKI, but PCM1808-Q1 does require SCKI even in slave mode.  In this case, my customer will have 1/2 divider to make 384fs from 768fs to meet the requirement.  Do you have any requirements other than the ones shown in the datasheet on page 11 which shows only high/low pulse duration and duty cycle of SCKI?  It doesn't show others like jitter, rise/fall time etc.  Do you have recommendation circuit to generate 1/2 SCKI?

    I understand PCM1802/3/4 support 768fs, but those are all non Q1 devices.  They have to use PCM1804/08/60/61-Q1 if they need Q1 devices.

    Best Regards,

    Yoshikazu Kawasaki

  • 0 in reply to Yoshikazu Kawasaki
    TI__Mastermind 23050 points

    Hi Kawasaki-san,

    Yes you are right the other devices in the family are not automotive qualified so in that case if you want to stick with PCM1808-Q1 you will need the clock divider. 

    One classic method is to use a flip flop with feedback. This is a very easy way to create a binary divider which is all that is needed here. I would just recommend one that can operate at the needed frequency with rise/fall times around 10ns or less to help minimize the jitter. PCM1808-Q1 does not have an internal PLL, it relies on clock dividers and this means there is not a loop filter to help clean up the jitter of the incoming clock signal. I don't have a spec for this unfortunately but if you keep a 50% duty cycle clock with 10ns or less rise/fall time you should not have any issues!

    Best,

    Zak