PCM1808-Q1: rise time / fall time of LRCK and BCK

Hi,

Excessive rise and fall times can lead to an increase in the jitter since the edge may be sampled at slightly different points in time and this will degrade the noise performance of the device. It may also lead to somewhat higher power consumption on the digital rail. This device will be more sensitive to jitter since it does not include an integrated PLL, so if possible I would recommend using a clock buffer that can satisfy these timing requirements.

Best,

Zak