TLV320AIC3007: Audio is not working in salve mode

Hello Prasanth,

What do you mean by "Audio is not working"? Is there noisy audio or no audio at all? It does not make sense to me that you are getting the same register dump for both slave mode and master mode. The device needs to be configured as master in register 8. The contents of that register should not be the same for both cases. 

I was able to look at the PLL configuration and it seems as the the PLL is incorrectly configured. As denoted in register 102, PLL_CLKIN uses MCLK as the input clock. If MCLK is 12.2MHz, the PLL coefficients need to be as followed:

P = 1

R = 1

J = 8

D = 600

Register 2 also looks to be configured incorrectly. This is the divider used to divide Fsref. The configuration you provided shows this register set to Fsref/6. If 16kHz is the desired sampling rate, that means Fsref was set to 96kHz. Fsref must be either 48kHz or 44.1kHz. With the PLL coefficients provided above, register 2 needs to be set to 0x44 to divide 48kHz/3 to achieve a sampling rate of 16kHz. Let me know if these changes help. 

Regards,

Aaron

Hi Aaron,

Thank you for your inputs,I have changed the configuration still no audio at all.Please have a look on below dump data.

/mnt # i2cdump -f -y 0 0x18
        0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 00 00 44 91 60 00 00 0a 00 00 00 01 00 00 00 20    ..D?`..?...?...
10: 20 ff ff 00 78 78 00 78 78 02 00 fe 00 00 fe 00     ...xx.xx?.?..?.
20: 00 00 00 00 20 c0 00 00 40 40 00 00 00 2f 2f b1    .... ?..@@...//?
30: 00 00 00 0f 2f 2f af 00 00 00 0f 00 00 00 2f 2f    ...?//?...?...//
40: b1 0f 00 00 00 2f 2f af 0f f4 00 00 00 00 00 00    ??...//???......
50: 2f 2f 80 00 00 00 0b 00 00 00 2f 2f 80 0b de 0c    //?...?...//????
60: 00 02 00 00 00 00 02 00 00 00 00 00 00 00 00 00    .?....?.........
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: 00 00 44 91 60 00 00 0a 00 00 00 01 00 00 00 20    ..D?`..?...?...
90: 20 ff ff 00 78 78 00 78 78 02 00 fe 00 00 fe 00     ...xx.xx?.?..?.
a0: 00 00 00 00 20 c0 00 00 40 40 00 00 00 2f 2f b1    .... ?..@@...//?
b0: 00 00 00 0f 2f 2f af 00 00 00 0f 00 00 00 2f 2f    ...?//?...?...//
c0: b1 0f 00 00 00 2f 2f af 0f f4 00 00 00 00 00 00    ??...//???......
d0: 2f 2f 80 00 00 00 0b 00 00 00 2f 2f 80 0b de 0c    //?...?...//????
e0: 00 02 00 00 00 00 02 00 00 00 00 00 00 00 00 00    .?....?.........
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................

Thanks,

Prasanth

Hello Prasanth,

It also looks like you are intending to use LINE1L and LINE1R but the ADC's are powered down. Please write 0x04 to registers 19 and 22. Please let me know if there are still any issues. 

Regards,

Aarong

Hello Aarong,

Currently we are not using LINE1L and LINE1R lines for speaker.We have connected speaker to RIGHT_LOP line.Please have a look on below schematic for more details.

Hello Prasanth,

It looks as though the PLL is still not configured correctly. Register 4 should read 0x20 to set J = 6. For D = 600, register 5 should be 0x09 and register 6 should be 0x60. 

Can you also please probe BCLK, WCLK, MCLK, and DIN? Can you also measure the RIGHT_LOP pin and see if you are seeing a DC voltage?

Regards,
Aaron