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PCM1808: system clock status

Koyo Asaishi
Intellectual 1710 points
Part Number: PCM1808

Hi team,.

Customer input clock, which is generated by crystal, to SCKI and the input will be Hi-Z during stop.
Do they need pull up or pull down resister?
if so, could you give me proper value?

LRCK and BCK of this device is Schmitt triger input with 50kohm pull down resister in slave mode.
When system clock is stopped and this device is master mode, is the output of LRCK and BCK High level?

Best regards,
Koyo

  • 0
    TI__Intellectual 800 points

    Hi Koyo-san,

    Since our US application team is on Thanksgiving holiday therefore i'm responding on their behalf.

    Yes, we would recommend to use very weak pull-down the clock so avoid Hi-Z when crystal gets stop. This is to avoid any leakage current and also un-desired behavior due to Hi-Z output of crystal. The pull-down value can be used as weak enough based on the drive strength of crystal so that it won't affect the clock quality when crystal is turned-on. From PCM1808 point of view, we are fine even it is driven very weekly.

    If system clock is stopped suddenly when device is in master mode, I believe (though i'm not 100% sure), the output LRCK and BCK can stuck to either HIGH or LOW level depending upon at which specific moment during the operation the system clock gets stopped. I believe this can be easily tested on EVM or device if it available at customer. For more accurate answer on this we may need to wait till next week for our US application team back from holiday.

    Regards,

    Uttam

  • 0 in reply to Uttam Agarwal
    TI__Intellectual 1710 points

    Hi Uttam,

    Thanks for the answer on the behalf of US app team.

    Please let them know I want to know the value of the very weak pull-down to avoid Hi-Z.

    Best regards,
    Koyo

  • 0 in reply to Koyo Asaishi
    TI__Intellectual 800 points

    Hi Koyo-san,

    I would recommend the weak pull down value of 30Kohm or so. 

    Regards,

    Uttam