LMX2571: Analog FM modulation with SPI FAST write to deviation register

Hi Zoltan

1. Remember that ±75kHz gets reflected back up to the VCO frequency, and the maximum deviation at the VCO can't be too much or the device won't stay locked. VCO gain at midpoint is approximately 56MHz/V, charge pump is 0-2.5V range, assume a little under 2V (a maximum of around 80MHz) to play with at the VCO because some margin is required for temperature drift and charge pump linearity.
   
   The maximum achievable frequency deviation becomes a function of output frequency. Throughout the datasheet and application examples, the DEN value is always 2^24, but this is not strictly required - if you can arrange for the deviation of the N-divider to avoid any integer boundaries by offsetting the deviation range, DEN can be much smaller, even down to 2^16 if things work out perfectly (see https://www.ti.com/lit/an/snaa309/snaa309.pdf section 6.2).  Thus it is always possible to achieve one full FPD frequency of deviation at the VCO, as long as your application can support the output frequency at which this deviation can be achieved. But if you restrict the output frequency choice, you will necessarily also restrict the maximum achievable deviation, since the fractional numerator must always avoid overflow/underflow.
   
   If you must start with a constrained output carrier frequency:
   
   1. Multiply up the required deviation back to the VCO to ensure it does not exceed the VCO tuning range
   2. Determine a PFD/DEN ratio which supports the required deviation range. You already know the CHDIV1 * CHDIV2 required to achieve the output, and you will need to pick a prescaler value - fortunately there's only 2 or 4, so I recommend starting at 2 to give yourself the largest integer-N component and the highest modulator order (if needed) and falling back to 4 if no tenable options emerge. Set Table 32's equation 4 in the datasheet equal to 32767 and solve for DEN/FPD ratio.
   3. Figure out what PFD frequencies are achievable for the required DEN/FPD ratio. You know that DEN must be at least large enough that ±32768 numerator steps do not cross an integer-N boundary. This gets easier if you have a fixed possible set of values for your reference input, since this also implies a fixed possible set of PFD frequencies and only a few possible N-divides.
2. Datasheet 7.3.13 suggests you can write in FSK SPI FAST by using standard SPI timings. The SPI clock timing requirements suggest 100MHz is the fastest possible programming rate, so theoretically you could change R33 at a rate of 100MHz/25 (assume 24-bit registers + one CLK for LE high) = 4MHz. I think this would handily satisfy your 500kHz update rate.
   
   There's a spec in the datasheet about "Maximum FSK rate" at 100kbaud for 200kHz loop filter, but this is referring to true FSK instead of emulated FM. In your case, the FM will be heavily oversampled and the actual bandwidth of the signal is only the modulation bandwidth (150kHz) so the loop filter should be set to 300kHz or more to accommodate.

Regards,

Derek Payne

Thank you Derek for your detailed answers.

Best regards,

Zoltan