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Original question:

CDCLVP1204: IN_MUX switching time

CDCLVP1204: IN_SEL Switchover Time to Stabilize

Don Schelle
Expert 4150 points
Part Number: CDCLVP1204

Hello,

We're observing some odd behaviour with the CDCLVP1204 during input switch over.    Our system is as follows:

  • Both inputs are 156.25MHz
  • Both inputs are AC coupled (with 100nF caps) LVPECL signals and terminated with 50 Ohm resistors connected to the VAC_REF pin.   
    • Each set of 50Ohm resistors has a 0.1uF capacitor connected VAC_REF to GND.
  • The LVPECL output is terminated with 150Ohm resistors on each line to GND.
  • There is a 4.75KOhm pull-down resistor between IN_SEL and GND.
  • VCC = 3.3V

Note: We know that the input mux is not hitless, nor do we expect it to be.

When switching from Input 0 to Input 1, the switchover occurs in <10ns and the general "shape" of the switch over is as expected.   The yellow trace represents IN_SEL.   The green trace is the LVPECL output from the CDCLVP1204.

However, when switching from Input 1 to Input 0, the output is not as expected:

We see the differential output voltage droop considerably, and then "slowly" increase in magnitude to the desired steady-state value over approximately 200ns.

Some questions:

  1. Is this expected behaviour?
  2. What is the guaranteed maximum time before the outputs become stable after a switch-over?   

Don

  • 0
    TI__Intellectual 770 points

    Hi Don,

                 Apologies for the late reply. It does seem very strange that when you switch from Input 1 to Input 0, the output requires 100 ns to settle. To answer your questions:

    1. I cannot comment on whether this is expected or unexpected behavior as this will depend on the internal circuitry of the device. Since this is a very old device, it will take us same time to locate the design database and get back to you on the circuit design. Let us take this offline.

    2. Additionally, since the datasheet doesn't specify anything about settling time, there is no guaranteed maximum time as such. I suspect this will have to do with the internal circuitry of the device as well. 

    I will reach out to you for further clarification.

  • 0 in reply to Badarish
    TI__Guru** 108820 points

    Hi all,

    Let's close this post as it has been taken offline.

  • +1
    TI__Intellectual 770 points

    Hi,

         After taking a closer look at the internal circuitry of this device, i can confirm that this is expected behavior. There will be settling time associated with switching of IN_SEL. The reason for this settling is associated with the biasing circuitry to the clock input stages and the mux. The Mux and IN0 input stage share biasing and therefore whenever you switch from IN1 to IN0, there will be some time required for the clocks to settle. 

    1 us of settling time is a good ball-park but do note that this is not something guaranteed by characterization.

    Thanks,