• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 21 subscribers
  • Views 348 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04828: LMK04828 Schematic Review

Harika balla
Prodigy 80 points
Part Number: LMK04828

Hi sir,

In our design, we are using LMK04828 CLK Synthesizer to provide a clocks for RF-ADC & RF-DAC in RFSoC. Single LMK device with SYSREF as Feedback with Nested Dual Loopback. 

LMK INPUT:

TCXO: 10MHz LVCMOS (CLKIN 0)

VCXO: 100MHz LVPECL

LMK OUTPUT:

LVDS Outputs

DCLKOUTs: 150MHz

SDCLKOUTs: 3.125MHz

LMK04828_SCH.pdf

  • 0
    TI__Mastermind 28550 points

    Hello Harika,

    We'll review this week and get back with you.

    73,
    Timothy

  • 0
    TI__Genius 12560 points

    Hi Harika,

    Nested dual loopback configuration establishes a fixed deterministic phase relationship between input reference to each output signals. Attached is the application note to explain the criteria to keep 0-delay mode.   

    https://www.ti.com/lit/an/snaa294/snaa294.pdf

    If you would have deterministic phase requirement between reference clock and all clocks out, including SYSREF, you would need to have a re-look on your reference input frequency (10MHz).

    Your schematic looks good and recommend to follow the LMK04828EVM schematic for keeping the correct connection and correct components values, like C11 and C16 to 10nF.

    https://www.ti.com/lit/ug/snau145b/snau145b.pdf

    For LVDS output, place 560ohm resistor at ZU_PL_CLK_P/N, ZU_SYSREF_P/N and ZU_PL_SYSREF_P/N outputs.

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 80 points

    Hi Ajeet,

    Thank you for your reply.

     In the LMK04828 datasheet, have mentioned two termination schemes for LVDS outputs one the RX device with External Receiver termination and one more with internal receiver termination.

     ZU_PL_CLK_P/N, ZU_SYSREF_P/N, and ZU_PL_SYSREF_P/N for these LVDS outputs using External Receiver termination.

        

    Is it need to place 560ohm at the LMK output for both configurations irrespective of the above configurations in the diagram?

  • +1 in reply to Harika balla
    TI__Genius 12560 points

    Ok, If these signals are used with external termination, then go ahead with the 100ohm external resistor.

    Regards,
    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 80 points

    Hi Ajeet,

    Thank you for the reply.

     I have one more concern

    For the OSCIN or CLKIN inputs, for the LVPECL differential CLK input why 2 times AC coupling is required at both TX side and RX Side as mentioned in the datasheet?

  • 0 in reply to Harika balla
    TI__Genius 12560 points

    Hi Harika,

    LVPECL driver can have different termination resistors, which can produce some common mode voltage, whereas LMK0482x input voltage common mode is around 1.6V or 1.7V nominal (about VCC/2). To isolate the common mode voltage between them and to maintain the impedance matching, LVPECL format input requires AC coupling caps at both the end driver as well as LMK04828 (receiver side) input.

    Regards,

    Ajeet Pal