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CDCE72010: PLL configuration

Part Number: CDCE72010
Other Parts Discussed in Thread: DAC3283

Hi E2E,

Our customer would like to know the proper CDCE72010 PLL configuration, please see the query as follows:

I am using a CDCE72010 PLL, and it runs very very hot on my board. I found a similar post on the forum where if you use the PLL with certain settings or in a certain configuration, it will run very hot.
This heat is causing performance issues on my board with the clocks being generated by the PLL, so I wanted to post the settings that I am using, and which clocks I need to generate, and see if there was a more efficient setup I could use.

cdce72010_pll.c
/*
 * cdce72010_pll.c
 *
 *  Created on: Mar 30, 2018
 *      Author: alexlee
 */

#include <stdlib.h>
#include <stdio.h>
#include "xil_printf.h"
#include "sleep.h"
#include "fmc150.h"
#include "cdce72010_pll.h"

fmc_err_t pll_init()
{
	uint32_t dword;
	fmc_err_t rc;
	//Default register values
	uint32_t reg[13] = {
		0x00000000,
		0x00000001,
		0x00000002,
		0x00000003,
		0x00000004,
		0x00000005,
		0x00000006,
		0x00000007,
		0x00000008,
		0x00000009,
		0x004C013A, // reg 10 input and vxo divide counters
		0x00003EBB, // reg 11 - bit 0 and 1 primary and secondary div2 *was 3E8B now 3EBB
		0x0000000C};
	//Writeable bit mask
	uint32_t wrtbts[13] = {
		0xFFFFFFFF,
		0xFFFFFFFF,
		0xFFFFFFFF,
		0xFFFFFFFF,
		0xFFFFFFFF,
		0xFFFFFFFF,
		0xFFFFFFFF,
		0xFFFFFFFF,
		0xFFFFFFFF,
		0xFFFFFFFF,
		0xFFFFFFFF,
		0x3FFFFFFF,
		0x0000180F};

	///////////////////////////////////////////////////////////////////////////////////////////////////////////


	printf("Configure PLL for 800 MHz, with 20 MHz external reference\n");

	///////////////////////////////////////////////////////////////////////////////////////////////////////////
	//check <REVISION> field
	rc = read_fmc_reg(PLL_REG12, &dword);
	if(rc!=FMC150_ERR_OK)
		return rc;
	dword = (dword & 0x0001C000)>>14;
	if (dword!=FMC150_CLOCKTREE_PART_REV)
		return FMC150_CLOCKTREE_ERR_WRONG_PART_REV;

	///////////////////////////////////////////////////////////////////////////////////////////////////////////
	//
	//
	//INFO: The lowest 4 bits of each command word are used for addressing, so each bit shift below should be reduced
	//by 4 to compare against the chip's data sheet. For example, reg[0] += 1<<6 is actually setting the 2nd bit in reg[0]
	//not the sixth.

	///////////////////////////////////////////////////////////////////////////////////////////////////////////
	// Common register settings
	reg[0] += 0x3<<4;		//INBUFSEL (was 1 10-LVPECL now 3 11-LVDS)
	reg[0] += 1<<6;		    //PRISEL
	//reg[0] += 0<<7;		//SECSEL
	reg[0] += 0<<8;			//VCXOSEL
	reg[0] += 1<<9;			//REFSELCNTRL
	reg[0] += 0<<10;		//DELAY_PFD
	reg[0] += 0<<12;		//CP_MODE
	reg[0] += 0<<13;		//CP_DIR
	reg[0] += 0<<17;		//CP_PRE
	reg[0] += 0xF<<18;		//ICP
	reg[0] += 0<<25;		//PECL0HISWING: disabled
	reg[0] += 0x1A<<26;		//Output 0: disabled (unused)

	reg[1] += 0<<4;			//AC coupled - ACDCSEL
	reg[1] += 1<<5;			//HYSTEN
	reg[1] += 0<<6;			//TERMSEL
	reg[1] += 0<<7;			//PRIINVBB
	reg[1] += 0<<8;			//SECINVBB
	reg[1] += 0<<9;			//FAILSAFE
	reg[1] += 0<<10;		//PH1ADJC
	reg[1] += 0<<17;		//OUT1DIVRSEL
	reg[1] += 0<<24;		//EN1DIV: disabled
	reg[1] += 0<<25;		//PECL1HISWING: disabled
	reg[1] += 0x1A<<26;		//Output 1: disabled (unused)

	//********LVPECL to ADC, 80 MHz, div 10
	reg[2] += 0<<4;			//DLYM
	reg[2] += 0<<7;			//DLYN
	reg[2] += 0<<10;		//PH2ADJC
	reg[2] += 0x03<<17;		//out2divrsel: divide by 10
	reg[2] += 1<<24;		//EN2DIV: enabled
	reg[2] += 1<<25;		//PECL2HISWING: enabled
	reg[2] += 0x1A<<26;		//Output 2: LVPECL to ADC (was x20 to enable)
	//************************************

	reg[3] += 0<<4;			//DIS_FDET_REF: on
	reg[3] += 0<<6;			//BIAS_DIV01: no current reduction
	reg[3] += 0<<8;			//BIAS_DIV23: no current reduction
	reg[3] += 0<<10;		//PH3ADJC
	reg[3] += 0<<17;		//OUT3DIVRSEL
	reg[3] += 0<<24;		//EN3DIV: disabled
	reg[3] += 0<<25;		//PECL3HISWING: disabled
	reg[3] += 0x1A<<26;		//Output 3: disabled (unused)

	//********LVDS to FPGA, 400 MHz, div 2 (NOW AUX CLK)
	reg[4] += 0<<8;			//HOLDONLOR
	reg[4] += 0<<10;		//PH4ADJC
	reg[4] += 0x40<<17;		//OUT4DIVRSEL: divide by 2
	reg[4] += 1<<24;		//EN4DIV: enabled
	reg[4] += 0<<25;		//PECL4HISWING: disabled
	reg[4] += 0x3A<<26;		//Output 4: LVDS to FPGA (x1A to disable)
	//************************************

	reg[5] += 0<<4;			//BIAS_DIV45: no current reduction
	reg[5] += 0<<6;			//BIAS_DIV67: no current reduction
	reg[5] += 0<<10;		//PH5ADJC
	reg[5] += 0<<17;		//OUT5DIVRSEL
	reg[5] += 0<<24;		//EN5DIV: disabled
	reg[5] += 0<<25;		//PECL5HISWING: disabled
	reg[5] += 0x1A<<26;		//Output 5: disabled (clock out)
	//********LVPECL, 25 MHz, div 32 to DAC 			    *** new additions by dortigoza
	reg[6] += 0<<4;			//FB_FD_DESEL
	reg[6] += 0<<6;			//FBDETERM_DIV_SEL
	reg[6] += 0<<7;			//FBDETERM_DIV2_DIS
	reg[6] += 0<<8;			//FB_START_BYPASS
	reg[6] += 0<<9;			//DET_START_BYPASS
	reg[6] += 0<<10;		//PH6ADJC
	reg[6] += 0xE<<17;		//OUT6DIVRSEL					*new (x1C 32' div) xE=32 x1=8 (100mhz)
	reg[6] += 1<<24;		//EN6DIV: enabled               *new was 0
	reg[6] += 1<<25;		//PECL6HISWING: enabled         *new was 0
	reg[6] += 0x1A<<26;		//Output 6: LVPECL to DAC       *new *was x20 to enable

	//********LVPECL to DAC, 800 MHz, div 1
	reg[7] += 0<<4;			//LOCKW
	reg[7] += 3<<7;			//LOCKC
	reg[7] += 0<<9;			//ADLOCK; digital Pll lock
	reg[7] += 0<<10;		//PH7ADJC

	reg[7] += 0x20<<17;		//OUT7DIVRSEL: divide by 1
	reg[7] += 1<<24;		//EN7DIV: enabled
	reg[7] += 1<<25;		//PECL7HISWING: enabled
	reg[7] += 0x20<<26;		//Output 7: LVPECL to DAC
	//************************************

	reg[8] += 1<<4;			//VCXOBUFSEL: LVPECL
	reg[8] += 0<<6;			//VCXOACDCSEL: AC coupled termination
	reg[8] += 1<<7;			//VCXOHYSTEN: enabled
	reg[8] += 0<<8;			//VCXOTERMSEL: enabled
	reg[8] += 0<<9;			//VCXOINVBB: enabled
	reg[8] += 0<<10;		//PH8ADJC
	reg[8] += 0<<17;		//OUT8DIVRSEL
	reg[8] += 0<<24;		//EN8DIV: disabled
	reg[8] += 0<<25;		//PECL8HISWING: disabled
	reg[8] += 0x1A<<26;		//Output 8: disabled (unused)

	reg[9] += 0<<4;			//HOLDF: off
	reg[9] += 1<<6;			//HOLD#
	reg[9] += 0<<7;			//HOLDTR
	reg[9] += 0<<8;			//HOLD_CNT
	reg[9] += 0<<10;		//LOCKW
	reg[9] += 0<<12;		//NOINV_RESHOL_INT
	reg[9] += 0<<14;		//START_BYPASS
	reg[9] += 0<<15;		//INDET_BP
	reg[9] += 0<<16;		//PLL_LOCK_BP
	reg[9] += 0<<17;		//LOW_FD_FB_EN
	reg[9] += 1<<18;		//NPRESET_MDIV
	reg[9] += 0<<19;		//BIAS_DIV_FB: no current reduction
	reg[9] += 0<<21;		//BIAS_DIV89: no current reduction
	reg[9] += 0<<23;		//AUXINVBB
	reg[9] += 1<<24;		//DIS_AUX_Y9: disable AUXIN
	reg[9] += 0<<25;		//PECL9HISWING: disabled
	reg[9] += 0x1A<<26;		//Output 9: disabled (unused)


	reg[12] += 1<<11;		//PD#
	reg[12] += 1<<12;		//RESET#,HOLD#

	///////////////////////////////////////////////////////////////////////////////////////////////////////////
	// Program registers
	for (uint8_t i = 0; i < 13; i++)
	{
		rc = write_fmc_reg(CDCE72010_BASE_ADDR+4*i, reg[i]); usleep(2000); //Write
		if(rc!=FMC150_ERR_OK)
			return rc;
		rc = read_fmc_reg(CDCE72010_BASE_ADDR+4*i, &dword); //Read
		if(rc!=FMC150_ERR_OK)
			return rc;
		if( (dword&wrtbts[i]) != (reg[i]&wrtbts[i]) ) { //Check, but ignore read-only bits
			xil_printf("Clock Tree SPI Fault\n");
			return FMC150_CLOCKTREE_ERR_SPI_FAULT;
		}
	}

	//Check PLL_LOCK field (only when internal clock is chosen)
	printf("Waiting for PLL lock...");
	for (uint8_t i=0; i<10; i++)
	{
		rc = read_fmc_reg(PLL_REG12, &dword);
		if(rc!=FMC150_ERR_OK)
			return rc;
		if ((dword&0x400)!=0)
			break;
		printf(".");
		usleep(100000); //wait a while before next poll
	}
	printf("\n");
	if ((dword&0x400)==0)
	{
		printf("PLL could not lock\n");
		return FMC150_CLOCKTREE_ERR_NO_LOCK;
	}
	else
		printf("PLL locked\n");

	return FMC150_ERR_OK;

}

fmc_err_t adjust_adc_phase(uint8_t phase_setting) {
	fmc_err_t rc;
	uint32_t dword;
	uint32_t reg = 0x00000002;

	xil_printf("Setting ADC clock phase to %d\n", phase_setting);

	reg += 0<<4;			//DLYM
	reg += 0<<7;			//DLYN
	reg += phase_setting<<10;		//PH2ADJC
	reg += 0x03<<17;		//out2divrsel: divide by 10
	reg += 1<<24;		//EN2DIV: enabled
	reg += 1<<25;		//PECL2HISWING: enabled
	reg += 0x20<<26;		//Output 2: LVPECL to ADC

	rc = write_fmc_reg(CDCE72010_BASE_ADDR+4*2, reg); usleep(2000); //Write
	if(rc!=FMC150_ERR_OK)
		return rc;
	rc = read_fmc_reg(CDCE72010_BASE_ADDR+4*2, &dword); //Read
	if(rc!=FMC150_ERR_OK)
		return rc;
	if( (dword) != reg) {
		xil_printf("Clock Tree SPI Fault\n");
		return FMC150_CLOCKTREE_ERR_SPI_FAULT;
	}
	return FMC150_ERR_OK;
}

I am using an 800MHz crystal on the PLL and only need to generate 800 Mhz on channel 7 and 200 on channel 4. The input clock is 20M on the primary input

Your assistance is appreciated.

Regards,
Carlo

  • Hi Carlo,

    Checking internally to see who might know the root cause.

    Regards,
    Hao

  • Hi Carlo,

    We aren't aware of any particular setting that can make the power consumption very high. Can you measure the actual current consumption and check if it's much higher than the datasheet numbers?

    Regards,
    Hao

  • I am referring to this post:

    https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/617165/cdce72010-cdce72010-on-ads5562evm---overheating-currently-running-with-200mhz-xo

    There was another post that seems to be missing now where the Applications engineer asked to see the device configuration....

    I cannot measure current on the device as it is soldered down to my board in a working circuit, but I can assure you this thing is running too hot. It runs hotter than my FPGA and all it is doing is making 2 clocks.

    Could you please look over my configuration and divider setup to see where I can reduce power on this?

  • Hi David,

    We are not sure on the register settings, which may responsible for heating the device. But we can help to debug the issue.

    Can you please provide the details on below:

    1. Are you seeing the device temp rise for other same boards also?

    2. Before programming, is there any temp change on the board?

    3. Is the PLL lock after programming (Lock detect status)?

    4. At a first glance, your configurations looks good but see some deviations from your text above. Please clarify the same:

    i) There are 4 output clocks from channel 2, 4, 6 and 7 with /10, /2, /32 and /1 divider configuration respectively.

    ii) Why the R0 [3] is not writing?

    iii) Register settings not mentioned for the reserved bits detail, those should be set to '0'. Are those bits writing '0'?

    iv) Is the readback working on your board? please verify the writing and readback data are same.

    Regards,

    Ajeet Pal

  • 1) I am seeing the temp in the range of 70C for all boards

    2) Before programming the part is cooler. I suspect it is inefficient counter values that run this part hotter. I have adjusted some settings to reduce counter values and have run a faster reference clock into the part and it runs 10 C cooler....

    2a. Adjusting the counter values to cool the part made my 800MHz waveform worse affecting the DAC that uses this clock down stream worse. (Dac output waveform has 800 MHz jitter of 1.25ns) This is the crux of the problem. I want to make this clock as clean as possible. If we can find suitable settings that reduce this generated clock's jitter to a minimum I would like to try that first

    3) The PLL locks easily after programming. Putting a scope probe on this indicates that the PLL stays in lock. Adjusting some of the counter values had a negative effect on the PLL lock and the PLL was having a harder time locking with some settings.

    4) i) Even though I have divider settings on those other clocks, I have the output set to off. Wouldnt that save power in this case? I have since turned off those dividers as well.

    ii) Strange. I will uncomment that. 

    iii) What is the reverse bits register?

    iv) readback does work as the FPGA code polls digital lock status after config.

    Some detail on 2a) I am using a DAC3283 on my board that requires the 800 MHz LVPECL core clock. When looking at the clock from the CDCE PLL on an oscilloscope I cannot tell any difference in settings in degredation in either voltage level or Jitter performance, HOWEVER the DAC generating a waveform downstream has about a 1/1000 jitter of 1.25ns, telling me something is wrong with this 800MHz clock. Playing with the counter settings and adjustiting the reference clock going into the CDCE PLL can make this WORSE. 

    I am looking for optimal settings for this waveform and such that the CDCE PLL will not be affected by temperature variation. If I blow air on the PLL circuit I can exasperate this issue further. If I cool the PLL with a heatsink and constant steady-state air cooling I can get the jitter to happen less frequently (about 1/10000 cycles)

    Part number for the VXO: ECXV-P37C2M-800.000

    Filter values according to figure 34 of the datasheet:

    C1 - 0.1uF

    R2 and C2 - 4.7K and 22uF

    R3 - 160ohm

    C3 - 0.1uF

  • Hi David,

    In your settings, you are using feedback divider with its full range (80) and as you mentioned above, while reducing the counter, temperature got down by 10 C. Are you reducing the feedback divider or N divider?

    I would be suggesting to try reducing the feedback divider to lower value and increase the N -divider for feedback section with the fixed M-divider (20) and see the performance.

    Higher phase detector frequency helps to improve the jitter performance. Hence you can try with increase the phase detector frequency.

    About the reserved bits, some of the registers having fixed reserved bits, those suppose to be set as per datasheet recommendation. Follow the each register settings.

    REG0:

    REG4 and others too...

    Regards,
    Ajeet Pal

  • Hello Ajeet,

    According to our customer, the new settings are not helping and are making this worse. The customer reduced Feedback counter from 80 to 10, (increased N counter to compensate) and doubled PFD frequency from 500K to 1M and the clock is much less stable. Please help.

    Regards,
    Carlo

  • Hi David, Carlo,

    I have updated the register settings with the following details:

    1. Disable the High Output Voltage Swing in LVPECL/LVDS Mode and dividers for all disabled outputs

    2. DIS_AUX_Y9 bit set to R9[20] = 0 

    3. Make Input buffer disable (PRI_DIV2 & SEC_DIV2) R11[1:0] = 00 and reduced feedback P-divider value to 40.

    REG0 683C0270
    REG1 68000021
    REG2 68060002
    REG3 68000003
    REG4 E9800004
    REG5 68000005
    REG6 681C0006
    REG7 83400187
    REG8 68000018
    REG9 680400C9
    REGA 004C013A
    REGB 00001E8B
    REGC 0000180C

    Currently, I don't have the HW setup to validate these setting and you can try in your setup and let me know the performance.

    Further you can test with the increasing and decreasing the phase detector frequency.

    If you still see the issue, i would prefer to go through the schematic for this setup.

    Regards,

    Ajeet Pal

  • Hello Ajeet,

    Here is the response I received from our customer:

    The register settings you have provided do not help with the 800MHz clock jitter. With these settings, the PLL runs at 74C instead of 79-80C. This is still far too high if I am only producing one clock and all other clocks are disabled.
    I uploaded your registers as is and did not modify them.

    Attached is the schematic sheet for the PLL.
    According to this excel sheet which is provided with the CDCE PLL evaluation board, I should have plenty of stability in phase and gain margin. What are some target points I should be shooting for?

    CDCE72010_PLL_Calc_REVC.xls

    Regards,
    Carlo

  • Hi Carlo,

    Please allow some time to go through the schematic and will update you soon.

    Regards,

    Ajeet Pal

  • Hello Ajeet,

    Do we have an update on this?

    Regards,
    Carlo

  • Hi Carlo,

    Sorry for the delayed response.

    I don't see any issue in the schematic, it looks pretty well. Even from the programming wise it looks good with customer's setting as well as what I had provided.

    I would think of do few iterations on the board for debug. Please verify on the board:

    1. Schematic doesn't show the AC coupling caps at the DAC side and I assume it should be there. If not, then isolate the DAC clock and see the Temp variation.

    2. Turned OFF the both required output buffers one by one and both then observe the temp.

    3. Try to reduce the phase detector frequency by increasing the divider counters and tune the loop filter BW.

    Regards,

    Ajeet Pal

  • Hi Carlo,

    I would also be suggested to verify the thermal pads layout of the device to follow the layout recommendation mentioned in datasheet.

    If it doesn't follow the recommendation, that also may affect the heating performance.

    Regards,

    Ajeet Pal