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Original question:

CDCVF2310: CDCVF2310

CDCVF2310: CDCVF2310

amnon pomerants
Intellectual 780 points
Part Number: CDCVF2310

Hi Jennifer,

Thanks again for your answers.

I would like to ask:

1. How do I calculate the minimum serial resistor that will keep current bellow rating of +/- 50mA,

    Is it 3.3V/ 50mA?  3.3V/ 100mA ? else ?

    I guess the "dark side" of this approach is having a termination resistor out of SI rules (>>50ohm) , no?

2. How comes a larger resistor is better for SI? The RC will increase and rise time will increase.

    Are you "afraid" the OSC increased output current will ruin the clock SI? It can drive 12mA, 3.3V/ 2.5K =~ 1.5mA should not be a problem, no ?

looking forward to hear from you

Thanks

Amnon

  • 0
    TI__Genius 12075 points

    Hello Amnon,

    Sorry, the 'original question' linked is confusing me, I think you are referring to your past question CDCVF2310: OSC at 3.3V driving CDCVF2310 at 2.5V.

    OSC Vdd requires 3.3V and FPGA requires 2.5V input clock - you essentially have 3 options associating with question 1 and 2:

    1. Give 3.3V to CDCCVF2310 operating at 2.5V making sure not to go over clamp current specification - +/-50mA.

    To calculate the minimum serial resistor that will keep current clamp rating below +/- 50mA you require 3.3V / 50mA = 66ohms. (Keep in mind the CDCVF2310 utilizes an on-chip 25ohms, therefore 66ohms - 25ohms = 41ohms) As stated, the Signal Integrity will be compromised as reflections will be induced.

    2. Utilize a voltage divider of passive components to reach optimal level of 2.5V.

    The largest component of this shift is using a capacitor voltage divider to shift from 3.3V AC to 2.5V AC - this then requires to re-center the voltage. It is during this re-centering that you need to be conscientious of the bandwidth settings of your device, rise time and fall time will also be. This painful approach can be avoided by utilizing option #3... 

    3. Utilize a level shifter to 2.5V to give proper 2.5V input to CDCVF2310 or try utilizing a ClockGen from our product portfolio.

    A ClockGen is going to offer better jitter performance and some devices have a built in function to offer different voltage levels - 2.5V.

    As you can see you have options, but it might be easier to utilize an alternate ClockGen that fits the application demand.

    Hopefully this helps!