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Hello!
I need someone to help me to check my design of the CDCLVD1208 clock buffer.
1) Input clock is 100MHz LVDS diff clock type,
2) Fanout 8 channels LVDS output clock, i use 7 channels LVDS output clock, (5 channels LVDS clock type, 2 channel LVPECL clock type)
3) My questions:
We ref TI some docs to add the pullup resisters to VCC, and add pulldown resisters to GND, convert the LVDS clock type to LVPECL type;
How can i choose the value of the pulldown and pullup resisters and the VCC ?
Hello,
We recommend using the following configuration for Vcc = 3.3V (figure from this apps note). This is the resistor combination we typically suggest though you may confirm by simulating with the IBIS model.
Regards,
Jennifer
In the recommended circuit, Zo is 50 ohm impedance. Is it feasible if we use 100 ohm differential impedance control?
The recommended value of VCC is 3.3V, and the working voltage of cdclvd1208 is 2.5V. What is the impact here?
Hi,
You may use 100 ohm across the outputs. VCC = 2.5V may be used.
Regards,
Jennifer