This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04616: Cannot generate pulsed SYSREF

Part Number: LMK04616

I am using LMK04616 clock gen and am unable to produce a pulsed SYSREF. I can produce a continuous SYSREF but neither pulsed over SPI nor via the SYNC pin has worked so far. I have followed the guidance on the forum here: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/730208/lmk04616-sysref-spi-trigger-problem?tisearch=e2e-sitesearch&keymatch=LMK04616%2525252520sysref# but so far no luck. I can generate the rest of my clocks just fine. I have attached my initialisation data for producing 5 pulses over SPI on channels 0/1 and 4/5, I then write to reg 0x014 bit 5 to initiate the burst of pulses. When I read back these registers they are as I would expect. Can anyone advise?

lmk04616_regs_5_sysref_pulses_over_spi.txt
R0	0x000000
R1	0x000100
R2	0x000200
R3	0x000306
R4	0x000438
R5	0x000503
R6	0x000615
R8	0x000800
R9	0x000900
R10	0x000A00
R12	0x000C51
R13	0x000D08
R16	0x00101F
R18	0x001206
R19	0x001310
R20	0x001402
R21	0x001508
R22	0x001650
R23	0x001719
R24	0x001802
R25	0x00190B
R26	0x001A0C
R27	0x001B00
R28	0x001C02
R29	0x001D00
R30	0x001E64
R31	0x001F00
R32	0x002064
R33	0x002100
R34	0x002264
R35	0x002314
R36	0x002480
R37	0x002514
R38	0x002680
R39	0x002714
R40	0x002880
R41	0x002914
R42	0x002A80
R43	0x002B00
R44	0x002C10
R45	0x002D00
R46	0x002E1E
R47	0x002F01
R48	0x003001
R49	0x003100
R50	0x003200
R51	0x003310
R52	0x003403
R53	0x003510
R54	0x003603
R55	0x003700
R56	0x003843
R57	0x003900
R58	0x003A03
R59	0x003B00
R60	0x003C43
R61	0x003D14
R62	0x003E03
R63	0x003F00
R64	0x004003
R65	0x004100
R66	0x004203
R67	0x004300
R68	0x004420
R69	0x004500
R70	0x004604
R71	0x004700
R72	0x004820
R73	0x004900
R74	0x004A08
R75	0x004B00
R76	0x004C04
R77	0x004D00
R78	0x004E1E
R79	0x004F00
R80	0x005008
R81	0x005100
R82	0x005208
R83	0x005300
R84	0x005410
R85	0x005500
R86	0x00561A
R87	0x005700
R88	0x00583F
R89	0x005930
R90	0x005A0A
R91	0x005B32
R92	0x005C0E
R93	0x005D00
R94	0x005E01
R95	0x005F84
R96	0x006080
R97	0x006100
R98	0x006219
R99	0x006300
R100	0x006440
R101	0x006500
R102	0x006600
R103	0x006700
R104	0x006800
R105	0x006900
R106	0x006A00
R107	0x006B01
R108	0x006C00
R109	0x006D2C
R110	0x006E1B
R111	0x006F00
R112	0x007000
R113	0x007100
R114	0x007214
R115	0x007300
R116	0x007420
R117	0x007500
R118	0x007601
R119	0x007701
R120	0x0078FF
R121	0x007900
R122	0x007A86
R123	0x007BA0
R124	0x007C08
R125	0x007D00
R126	0x007E00
R127	0x007F34
R128	0x008000
R129	0x008100
R130	0x008200
R131	0x008300
R132	0x00840F
R133	0x008501
R134	0x008601
R135	0x008700
R136	0x008840
R137	0x008900
R138	0x008A00
R139	0x008B40
R140	0x008C00
R141	0x008D00
R142	0x008E00
R143	0x008F40
R144	0x009000
R145	0x009100
R146	0x009281
R147	0x009382
R148	0x009404
R149	0x009512
R150	0x009610
R151	0x009760
R152	0x009820
R153	0x009980
R155	0x009B00
R156	0x009C20
R157	0x009D00
R158	0x009E00
R159	0x009F00
R160	0x00A000
R161	0x00A100
R162	0x00A200
R163	0x00A300
R164	0x00A400
R165	0x00A500
R166	0x00A600
R167	0x00A700
R168	0x00A800
R169	0x00A900
R170	0x00AA00
R171	0x00AB00
R172	0x00AC00
R173	0x00AD00
R174	0x00AE00
R175	0x00AF00
R176	0x00B001
R177	0x00B100
R178	0x00B200
R179	0x00B300
R180	0x00B402
R181	0x00B500
R182	0x00B600
R183	0x00B700
R184	0x00B800
R185	0x00B900
R186	0x00BA3F
R187	0x00BB0F
R188	0x00BC50
R189	0x00BD00
R190	0x00BE02
R191	0x00BF00
R192	0x00C000
R193	0x00C100
R194	0x00C200
R195	0x00C300
R196	0x00C400
R197	0x00C500
R198	0x00C600
R199	0x00C700
R200	0x00C800
R201	0x00C900
R202	0x00CA00
R203	0x00CB00
R204	0x00CC00
R205	0x00CD00
R206	0x00CE00
R207	0x00CF00
R208	0x00D000
R209	0x00D100
R210	0x00D200
R211	0x00D300
R212	0x00D400
R213	0x00D500
R214	0x00D600
R215	0x00D700
R216	0x00D800
R217	0x00D900
R218	0x00DA00
R219	0x00DB00
R220	0x00DC00
R221	0x00DD00
R222	0x00DE00
R223	0x00DF00
R224	0x00E000
R225	0x00E100
R226	0x00E200
R227	0x00E300
R228	0x00E400
R229	0x00E500
R230	0x00E600
R231	0x00E700
R232	0x00E800
R233	0x00E900
R234	0x00EA00
R235	0x00EB00
R236	0x00EC00
R237	0x00ED00
R238	0x00EE00
R239	0x00EF00
R240	0x00F000
R241	0x00F100
R242	0x00F200
R243	0x00F300
R244	0x00F400
R245	0x00F500
R246	0x00F600
R247	0x00F700
R248	0x00F800
R249	0x00F906
R250	0x00FAD7
R252	0x00FC00
R253	0x00FD00
R254	0x00FE00
R255	0x00FF00
R256	0x010000
R257	0x010100
R258	0x010200
R259	0x010300
R260	0x010400
R261	0x010500
R262	0x010600
R263	0x010700
R264	0x010800
R265	0x010900
R266	0x010A00
R267	0x010B00
R268	0x010C00
R269	0x010D00
R270	0x010E00
R271	0x010F00
R272	0x011000
R273	0x011100
R274	0x011200
R275	0x011300
R276	0x011400
R277	0x011500
R278	0x011600
R279	0x011700
R280	0x011800
R281	0x011900
R282	0x011A00
R283	0x011B00
R284	0x011C00
R285	0x011D00
R286	0x011E00
R287	0x011F00
R288	0x012000
R289	0x012100
R290	0x012200
R291	0x012300
R292	0x012401
R293	0x012500
R294	0x012600
R295	0x012705
R296	0x012805
R297	0x012905
R298	0x012A05
R299	0x012B05
R300	0x012C05
R301	0x012D05
R302	0x012E05
R303	0x012F00
R304	0x013000
R305	0x013100
R306	0x013200
R307	0x013300
R308	0x013400
R309	0x013500
R310	0x013600
R311	0x013700
R312	0x013800
R313	0x013900
R314	0x013A00
R315	0x013B00
R316	0x013C00
R317	0x013D00
R318	0x013E00
R319	0x013F00
R320	0x014005
R321	0x014112
R322	0x014260
R323	0x014300
R324	0x014400
R325	0x014500
R326	0x01463C
R327	0x014700
R328	0x014800
R329	0x014900
R330	0x014A00
R331	0x014B00
R332	0x014C00
R334	0x014E05
R335	0x014F00
R336	0x015000
R337	0x015100
R338	0x015200
R339	0x015300
R17	0x001101

  • Hello Genevieve,

    I put together a flowchart discussing SYSREF generation a long time ago. I've included it below.

    6864.LMK0461x Divider Reset Flowchart.pdf

    The final page is the flowchart specifically for generating the SYSREF event. The preceding pages discuss divider synchronization i.e. aligning SYSREF phase to device clock phase.

    Regards,

    Derek Payne

  • Hi Derek, thank you for this. This is a great reference guide, but unfortunately I am still unable to generate individual pulses. Is it possible to use our initialisation config and independently verify whether this setup works for you? I've attached my latest file for generating one pulse over SPI.

    lmk04616_regs_1_sysref_pulse_over_spi.txt
    R0	0x000000
    R1	0x000100
    R2	0x000200
    R3	0x000306
    R4	0x000438
    R5	0x000503
    R6	0x000615
    R8	0x000800
    R9	0x000900
    R10	0x000A00
    R12	0x000C51
    R13	0x000D08
    R16	0x00101F
    R18	0x001206
    R19	0x001308
    R20	0x001402
    R21	0x001508
    R22	0x001650
    R23	0x001719
    R24	0x001802
    R25	0x00190B
    R26	0x001A0C
    R27	0x001B00
    R28	0x001C02
    R29	0x001D00
    R30	0x001E64
    R31	0x001F00
    R32	0x002064
    R33	0x002100
    R34	0x002264
    R35	0x002314
    R36	0x002480
    R37	0x002514
    R38	0x002680
    R39	0x002714
    R40	0x002880
    R41	0x002914
    R42	0x002A80
    R43	0x002B00
    R44	0x002C10
    R45	0x002D00
    R46	0x002E1E
    R47	0x002F01
    R48	0x003001
    R49	0x003100
    R50	0x003200
    R51	0x003310
    R52	0x003443
    R53	0x003510
    R54	0x003603
    R55	0x003710
    R56	0x003843
    R57	0x003900
    R58	0x003A03
    R59	0x003B00
    R60	0x003C43
    R61	0x003D14
    R62	0x003E03
    R63	0x003F00
    R64	0x004003
    R65	0x004100
    R66	0x004203
    R67	0x004300
    R68	0x004420
    R69	0x004500
    R70	0x004604
    R71	0x004700
    R72	0x004820
    R73	0x004900
    R74	0x004A08
    R75	0x004B00
    R76	0x004C04
    R77	0x004D00
    R78	0x004E1E
    R79	0x004F00
    R80	0x005008
    R81	0x005100
    R82	0x005208
    R83	0x005300
    R84	0x005410
    R85	0x005500
    R86	0x00561A
    R87	0x005700
    R88	0x00583F
    R89	0x005930
    R90	0x005A0A
    R91	0x005B32
    R92	0x005C0E
    R93	0x005D00
    R94	0x005E01
    R95	0x005F84
    R96	0x006080
    R97	0x006100
    R98	0x006219
    R99	0x006300
    R100	0x006440
    R101	0x006500
    R102	0x006600
    R103	0x006700
    R104	0x006800
    R105	0x006900
    R106	0x006A00
    R107	0x006B01
    R108	0x006C00
    R109	0x006D2C
    R110	0x006E1B
    R111	0x006F00
    R112	0x007000
    R113	0x007100
    R114	0x007214
    R115	0x007300
    R116	0x007420
    R117	0x007500
    R118	0x007601
    R119	0x007701
    R120	0x0078FF
    R121	0x007900
    R122	0x007A86
    R123	0x007BA0
    R124	0x007C08
    R125	0x007D00
    R126	0x007E00
    R127	0x007F34
    R128	0x008000
    R129	0x008100
    R130	0x008200
    R131	0x008300
    R132	0x00840F
    R133	0x008501
    R134	0x008601
    R135	0x008700
    R136	0x008840
    R137	0x008900
    R138	0x008A00
    R139	0x008B40
    R140	0x008C00
    R141	0x008D00
    R142	0x008E00
    R143	0x008F40
    R144	0x009000
    R145	0x009100
    R146	0x009281
    R147	0x009382
    R148	0x009404
    R149	0x009512
    R150	0x009610
    R151	0x009760
    R152	0x009820
    R153	0x009980
    R155	0x009B00
    R156	0x009C20
    R157	0x009D00
    R158	0x009E00
    R159	0x009F00
    R160	0x00A000
    R161	0x00A100
    R162	0x00A200
    R163	0x00A300
    R164	0x00A400
    R165	0x00A500
    R166	0x00A600
    R167	0x00A700
    R168	0x00A800
    R169	0x00A900
    R170	0x00AA00
    R171	0x00AB00
    R172	0x00AC00
    R173	0x00AD00
    R174	0x00AE00
    R175	0x00AF00
    R176	0x00B001
    R177	0x00B100
    R178	0x00B200
    R179	0x00B300
    R180	0x00B402
    R181	0x00B500
    R182	0x00B600
    R183	0x00B700
    R184	0x00B800
    R185	0x00B900
    R186	0x00BA3F
    R187	0x00BB0F
    R188	0x00BC50
    R189	0x00BD00
    R190	0x00BE02
    R191	0x00BF00
    R192	0x00C000
    R193	0x00C100
    R194	0x00C200
    R195	0x00C300
    R196	0x00C400
    R197	0x00C500
    R198	0x00C600
    R199	0x00C700
    R200	0x00C800
    R201	0x00C900
    R202	0x00CA00
    R203	0x00CB00
    R204	0x00CC00
    R205	0x00CD00
    R206	0x00CE00
    R207	0x00CF00
    R208	0x00D000
    R209	0x00D100
    R210	0x00D200
    R211	0x00D300
    R212	0x00D400
    R213	0x00D500
    R214	0x00D600
    R215	0x00D700
    R216	0x00D800
    R217	0x00D900
    R218	0x00DA00
    R219	0x00DB00
    R220	0x00DC00
    R221	0x00DD00
    R222	0x00DE00
    R223	0x00DF00
    R224	0x00E000
    R225	0x00E100
    R226	0x00E200
    R227	0x00E300
    R228	0x00E400
    R229	0x00E500
    R230	0x00E600
    R231	0x00E700
    R232	0x00E800
    R233	0x00E900
    R234	0x00EA00
    R235	0x00EB00
    R236	0x00EC00
    R237	0x00ED00
    R238	0x00EE00
    R239	0x00EF00
    R240	0x00F000
    R241	0x00F100
    R242	0x00F200
    R243	0x00F300
    R244	0x00F400
    R245	0x00F500
    R246	0x00F600
    R247	0x00F700
    R248	0x00F800
    R249	0x00F906
    R250	0x00FAD7
    R252	0x00FC00
    R253	0x00FD00
    R254	0x00FE00
    R255	0x00FF00
    R256	0x010000
    R257	0x010100
    R258	0x010200
    R259	0x010300
    R260	0x010400
    R261	0x010500
    R262	0x010600
    R263	0x010700
    R264	0x010800
    R265	0x010900
    R266	0x010A00
    R267	0x010B00
    R268	0x010C00
    R269	0x010D00
    R270	0x010E00
    R271	0x010F00
    R272	0x011000
    R273	0x011100
    R274	0x011200
    R275	0x011300
    R276	0x011400
    R277	0x011500
    R278	0x011600
    R279	0x011700
    R280	0x011800
    R281	0x011900
    R282	0x011A00
    R283	0x011B00
    R284	0x011C00
    R285	0x011D00
    R286	0x011E00
    R287	0x011F00
    R288	0x012000
    R289	0x012100
    R290	0x012200
    R291	0x012300
    R292	0x012401
    R293	0x012500
    R294	0x012600
    R295	0x012705
    R296	0x012805
    R297	0x012905
    R298	0x012A05
    R299	0x012B05
    R300	0x012C05
    R301	0x012D05
    R302	0x012E05
    R303	0x012F00
    R304	0x013000
    R305	0x013100
    R306	0x013200
    R307	0x013300
    R308	0x013400
    R309	0x013500
    R310	0x013600
    R311	0x013700
    R312	0x013800
    R313	0x013900
    R314	0x013A00
    R315	0x013B00
    R316	0x013C00
    R317	0x013D00
    R318	0x013E00
    R319	0x013F00
    R320	0x014001
    R321	0x014112
    R322	0x014260
    R323	0x014300
    R324	0x014400
    R325	0x014500
    R326	0x01463C
    R327	0x014700
    R328	0x014800
    R329	0x014900
    R330	0x014A00
    R331	0x014B00
    R332	0x014C00
    R334	0x014E05
    R335	0x014F00
    R336	0x015000
    R337	0x015100
    R338	0x015200
    R339	0x015300
    R17	0x001101
    

  • Hi Genevieve,

    Derek will respond soon to this. There was a holiday in the USA.

    regards,

    Julian

  • Genevieve,

    I don't have a 15.36MHz VCXO to test the configuration, so I substituted 122.88MHz VCXO with PLL1_N set to 200 and PLL2_R set to 4 to achieve the same 30.72MHz PFD frequency; otherwise all register settings were the same. In this configuration I had no trouble generating a SYSREF pulse by toggling the GLOBAL_SYSREF bit.

    Re-reading your description, I note that you say you are toggling 0x014 bit 5 (GLOBAL_CONT_SYSREF) which forces a continuous SYSREF output... but you refer to this as the trigger for your pulse train. Perhaps you meant to be writing 0x014 bit 4 (GLOBAL_SYSREF) instead?

    Regards,

    Derek Payne

  • Genevieve,

    We haven't heard from you in a week. I'm marking this thread as TI Thinks Resolved, but please let me know if additional assistance is required.

    Regards,

    Derek Payne