LMK04832: request for design review

Ranjini,

There are several problems with this configuration:

• LMK04832 cannot generate 1440MHz from internal VCO. An external VCO, a higher-frequency distribution mode clock at 1440MHz or 2880MHz, or a different device is required. I believe the LMK04828-EP has 2880MHz in range of VCO1, and this device is p2p compatible and nearly functionally identical with LMK04832 (though phase detector frequency would be cut to 120MHz rather than 180MHz).
• The least common multiple of 325MHz and 360MHz is 23.4GHz. No clock generator with a single PLL or only integer dividers can produce this frequency combination. If 325MHz is truly required in addition to the other frequencies, you require either a fractional output divider or a two-PLL device/system. The only TI device which supports both SYSREF and the desired frequency plan on a single chip is LMK5C33216, and this may be more complexity than what makes sense for your application. You could use another low-cost PLL to generate the 325MHz clocks from a fractional or low-integer PFD - something like LMX2572LP could generate a decent-quality 325MHz in integer mode with 80MHz PFD, and has the ability to synchronize the divider if for some reason you must synchronize the 325MHz clock to the LMK04828-EP SYSREF. I'm not exactly sure how or if you intend to link 36MHz SYSREF with 325MHz clocks, since the GCD of these clocks is 1MHz., but one of these clocks is labeled LMK_PL_SYSREF... is 325MHz actually the required frequency for these clocks? Do they actually require SYSREF?

Given the problems with using LMK04832, and the questions open around the design, I'll save my comments on the loop filter for a future iteration of the design.

Regards,

Derek Payne

Hi Derek,

Instead of 325MHz, we'll be using 360MHz. Will this be okay?

Hi Ajeet,

"To generate 1440M, 360M and 36M clocks out from LMK04828-EP should be good with 360MHz reference input". The part used in our design is LMK04832, our design is in final release stage . Will this part give us the required output?

Also we have tried simulating in TICS Pro, we were able to achieve this with LMK04832.

Hi Ajeet,

After analyzing the requirements, we have updated the frequency requirements in the schematic. Find the details below and please review the same & give your comments.

LMK_IN_CLK = 360Mhz

2705.SCHEMATIC _ LMK.pdf

Thanks & Regards,

Ranjini

HI Ajeet,

We have updated the frequency requirements. Find the details below and please review the same & give your comments.

LMK_IN_CLK = 360Mhz

WB_ADC_CLK - 1260MHz

SYSREF - 19.6875MHz (or multiple of same)

NB_ADC-CLK - 360MHz

MGTCLK - 315MHz

Thanks & Regards,

Ranjini