• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 583 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMK04828: Multi-board LMK Sync

LMK04828: LMK04828 Sync not stable at every Power-On

Shekhar Kulkarni
Intellectual 880 points
Part Number: LMK04828

Hi,

For LMK04828, we are using Dual Loop Mode with SYNC_POL toggle for SDCLK and DCLK phase determinism

Programming Procedure

1st: write all the registers in numeric order;

2nd: set SYSREF_MUX to Normal, and set SYNC_MUX to pin, turn on all the blocks and enable syncing of all clock outputs and then toggle SYNC_POL on-off-on, disable syncing of all clock output, set SYSREF_MUX to continuous:

But on every Power recycle we are getting different phase relation b/w outputs

Please provide some suggestion

  • 0
    TI__Mastermind 33710 points

    Hi Shekhar,

    The SYSREF local delays need to be cleared by setting SYSREF_CLR 0->1 before toggling SYNC_POL. Otherwise it seems you have performed the rest of the SYNC procedure correctly. Also, make sure that DCLKoutX_DDLY_PD=0 when performing the SYNC procedure, or the local delays on the device clock will not be applied. Finally, if you have an odd divide on the device clocks (1, 3, 5, ...), make sure DCLKoutX_MUX is set to use the duty cycle correction (DCC) feature.

    You also should defer programming of 0x168 until after programming registers up to 0x173, to ensure calibration happens after PLL2, PLL2 prescaler, and the VCO LDOs have powered up. Otherwise, you may not see lock across full operating temperature. This is unrelated to SYNC issues, but worth pointing out since you described writing all registers in "numeric order".

    Regards,

    Derek Payne