LMK04828: Start the SYSREF pulser from CLKin0

Victor,

Unfortunately no, this is a mistake in the datasheet. Only SYNC pin or SPI write can trigger pulser. This will be fixed in a subsequent datasheet revision.

Regards,

Derek Payne

Victor,

The only mistake in the datasheet diagram is that the pulser trigger path should be connected to the output of the SYNC_MODE mux directly, before the OR gate. CLKin0 and SYNC_MODE are both retimed to the clock distribution path on the "normal SYNC" path through the SYSREF_MUX. CLKin0 can also bypass the retimer and directly distribute onto the SYNC/SYSREF distribution path by changing the SYSREF_CLKin0_MUX setting.

I can predict some of the follow-up questions:

We have some data suggesting that the SYNC pin retiming to clock distribution path is reliable only to about 3-5ns and will vary by over 1ns across temperature and supply voltage. The circuitry on the SYNC pin timing is mostly CMOS, which has pretty large temperature dependency. If all you need is output-to-output alignment on one device, SYNC pin timing is not an issue. Using SYNC pin to try to synchronize multiple devices, or one device with an essential input-to-output phase relationship, against a GHz VCO on the clock distribution path is essentially guaranteed to fail without taking advantage of a more constraining configuration like zero-delay mode.

We also have some data suggesting that the CLKin0 port retiming is extremely precise, <150ps setup time and very limited variation across PVT. This path is all done in low-drift and low-noise bipolar circuits on a dedicated internal LDO, which is much less susceptible to timing variation. So if you're trying to do precise or multi-device synchronization against a GHz VCO, and cannot use any tactics to increase the valid SYNC window (e.g. zero-delay mode with the SYSREF divider to utilize the second DFF retimer), the CLKin0 port is the best method to use and will have significantly better timing precision than the SYNC pin.

There's an app note which discusses some techniques to reduce timing burden in synchronization: https://www.ti.com/lit/pdf/snaa294 

Also worth noting: once the SYSREF divider phase is locked in through the synchronization process, SYNC pin triggering (or even SPI triggering) of the SYSREF divider is often all you need, because the SYSREF pulser is implicitly retimed to the SYSREF divider edge which is almost always orders of magnitude slower than the clock distribution path frequency.

Regards,

Derek Payne