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Original question:

LMK05318B: Output divider sync from different PLL

LMK05318B: DPLL error flags and issues with OUT-7

Julian Dietrich
Prodigy 30 points
Part Number: LMK05318B
Other Parts Discussed in Thread: LMK05318

Hello TI,

we are facing several issues with LMK05318B.

1) We're not able to get rid of two error flags of DPLL: LOFL_DPLL and  LOPL_DPLL.
When the PLL is reprogrammed while run-time, LOFL_DPLL disappears, but LOPL_DPLL is always flagged.

2) After boot-up, OUT7 is never up. Reprogramming the PLL at run-time enables OUT-7.

Attached is our current configuration file. Would be nice, if TI could check this configuration and guide us in solving the issues.

Thanks in advance!

LMK05318_sync TDC BW 100Hz.tcs


  • 0
    TI__Expert 8585 points

    Hello Julian,

    There reason you are having issues with the DPLL locking is because your XO frequency is an integer multiple of the VCO1 frequency.

    In DPLL mode, the XO frequency must have a non-integer relationship to the VCO1 frequency so APLL1 can operate in fractional mode (required for proper DPLL operation).

    By changing your XO frequency to a non-integer multiple of the 2500 MHz frequency of VCO1, you will be able to solve the issues you are facing.

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Prodigy 30 points

    Hello Kia,

    thanks for your fast reply!

    I tried another configuration with disabled DPLL:


    Now I have a new error, flag (HLDOVR) and LOFL_DPLL and  LOPL_DPLL is always flagged.
    But I guess, I can neglect this, because I disabled the DPLL. Isn't it?

    Disabling the DPLL does not solve the issue with OUT-7. This output is still dead and can be enabled by just re-writing all registers after boot-up.

    Please give some more advise. Thanks!

  • +1 in reply to Julian Dietrich
    TI__Expert 8585 points

    Hello Julian,

    Yes, the HLDOVER, LOFL_DPLL, and LOPL_DPLL flags will always be high when the DPLL is not in use.

    As for the OUT7 issue, please try loading the configuration below. I regenerated the file and I can see OUT7 after re-writing all the registers after boot-up.

    LMK05318_sync TDC BW 100Hz (DPLL disabled).tcs

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Prodigy 30 points

    Hello Kia,

    I'm very sorry, but I mixed up OUT7 with OUT6. The issue with not running clock is on OUT6, not on OUT7!

    When I use your configuration, also OUT6 is up after boot-up, but only because your configuration do not set the SYNC-flags for this output:


    But we need to use that SYNC-Flag!

    When I use your configuration and additionally set the SYNC-Flag, OUT6 is not up after boot-up.

    Please verify on your side and give some advice. Thanks in advance!

  • +1 in reply to Julian Dietrich
    TI__Expert 8585 points

    Hello Julian,

    When the CHx_SYNC_EN bit is set, the SYNC_SW bit must be toggled for the synchronization to occur and for the outputs to be aligned. Once the SYNC_SW is toggled, the output will reappear. Here is an image of where the SYNC_SW control is located:

    Please load the configuration I provided you, enable the CHx_SYNC_EN bits that need to be enabled, toggle the SYNC_SW, and then save the configuration.

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Prodigy 30 points

    Hello Kia,

    thanks a lot again, now everything is clear now and running as required!

    I was just confused about OUT6 not running after boot-up, because OUT7 is always running after boot-up, even without a SYNC-event when the SYNC-flag is set.

    Last question: We now disabled the DPLL. Does it mean that I can also kick out the CLK-inputs on PRIREF and SECREF and only use the XO-inputs? 

  • 0 in reply to Julian Dietrich
    TI__Expert 8585 points

    Hello Julian,

    That is correct. You only need to use the XO input.

    Regards,

    Kia Rahbar