Part Number: CDCE6214
Other Parts Discussed in Thread: CLOCK-TREE-ARCHITECT, CDCM6208, LMK03318
Hello Team,
I am using CDCE6214 for clock generation on our board and TICS Pro SW 1.7.2 to create configuration file to control it.
Our board, and so TICS Pro configuration too, is provided with the following data parameters:
PLL Ref = 27MHz
SSC=DCO Mode= not enabled
OUT0=not enabled
OUT1=not Powerdown
OUT2=Powerdown
OUT3=Powerdown
OUT4=Powerdown
Channel Muxes=PSA
So, the only active output is OUT1.
Could you please explain why it seems not possible to set 176MHz output frequency with aformentioned parameters?
The SW seems to refuse to apply the input above and "Calculate Frequency Plan" button produce the following error message : "Error 0MHz cannot be gerated by existing prescaler / output divider values" , while for frequency below 176MHz and above 191MHz seems to work fine.
Also, please let me know why even changing the PLL Ref frequency seems not to allow the SW to work with this frequency(176MHz), am I missing something?
Thanks
Best Regards,
Fabio