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Original question:

CDCI6214: CDCI6214

CDCI6214: Jitter of two-divided frequency.

Shubiao Wang
Intellectual 1490 points
Part Number: CDCI6214

Hi there,

customer requirement: 

input 52Mhz LVDS CLK, output 26Mhz LVDS CLK, is it achievable by CDCI6214?

if yes, what's the expected jitter caused by CDCI6214?

BRs,
Shubiao

  • 0
    TI__Mastermind 33790 points

    Shubiao,

    Yes, this frequency plan can be achieved with CDCI6214. I would anticipate around 500-650fs RMS jitter 1kHz-20MHz when using the PLL. You could also bypass the PLL entirely and just use the device as a 1:4 LVDS fanout buffer/divide-by-2 block, which would have a noise floor around -158dBc/Hz - I can't estimate the jitter without knowing the reference characteristics.

    Regards,

    Derek Payne