HI Derek,
I posted a question regarding single shot sysref generation . I am just writing this to say the device is working and the reason from my problem is sysref was being sent to a my fpga via decoupling caps. This caused the input of the fpga to bias to the switch point. Every sysref clock edge (not the gated output) caused the a little spur which my poorly biased fpga picked up. I would have seen this earlier but have been working remotely for the last couple of years.
I just wanted to thank you for not dropping the problem even though I couldn't work out how to tell you id fixed it.
Many thanks
/Peter
