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Original question:

LMK04826: Synchronization between SYSCLK and SYSREF

LMK04826: Setup sequence for synchronization between SYSCLK and SYSREF

JH Shin
Guru 11260 points
Part Number: LMK04826


Hello,

My customer got the guide for synchronization between SYSCLK and SYSRE as link below.

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1086183/lmk04826-synchronization-between-sysclk-and-sysref/4021812#4021812

They asked TI to review the modified below setup sequence for synchronization between SYSCLK and SYSREF to ensure that there are no issues.

Note that continuous SYSREF mode is used.

   1. Write the register values in the following files created through TI GUI sequentially

        lmk04826_0.dat

  2. Wait until PLL2 is locked

  3. Write 0x144  ff  (sync dis : 1)

  4. Write 0x143 19  (sysref clr : 0)

  5. Write 0x139 03  (sysref continus)

Could you please review the register values and setup sequence for synchonization between SYSCLK and SYSREF?

Please let us know if there are any errors or corrections are required.

Thank you.

JH

  • 0
    TI__Genius 12560 points

    Hi JH,

    Your configuration file and updated sequence for synchronized output seems to be good. Once the PLL2 lock occurs, SYNC_PLL2_DLD generates the SYNC to reset the dividers, which are configured for SYNC reset ON.

    Thanks!

    Regards,

    Ajeet Pal