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LMX2615-SP: LMX2615-SP Programming Part using MSP430FR5969

Part Number: LMX2615-SP
Other Parts Discussed in Thread: MSP430FR5969, TPS7A4501-SP

Hello,

1. If I don't wanted to used PIN Mode and I have to controlled two LMX2615-SP with one controller MSP430FR5969 with following requirement then is it possible.?

a). We need phase synchronization between two output of  two different LMX2615-SP.

2. What is the optimum input power level if we used fosc frequency 50 MHz.?

3. Below is the LMX2615 board output when DC is in off condition. (Note: This board developed by us)

 

4.  Below is the LMX2615 board output when DC is in ON condition. (Note: This board developed by us)

during the ON Condition we got some low frequency hump.

Condition: Rest of the output port is 50 Ohm terminated.

Out of the two input we used only one and another one is terminated with 50 ohm.

Applied Voltage: 3.3 Volt and Current is 270 mA during ON condition. 

What is the reason for low freq. hump and how to rectify the problem. ?

  • Hi Nilesh,

    1. You can get phase synchronization between two LMX2615-SP... please check datasheet 7.3.12 and especially figure 26, which details the requirements and limitations of different configurations. Category 1 and 2 SYNC is straightforward, but category 3 sync may require a precisely timed SYNC pulse that arrives within the same OSCin cycle between the two devices (and this may require a retimer for the SYNC signal against OSCin)
    2. It depends on the waveshape. If the 50MHz is a sinewave, "as high as permitted into 50Ω load" based on the peak-to-peak maximum voltage value for single-ended inputs in the datasheet and the supply voltage constraints; if the 50MHz is a clipped-sine, or a square wave like LVDS/LVPECL, aim for somewhere between the minimum and maximum signal swing levels in the datasheet, and focus on keeping the slew rate as high as possible during the input reference transition from low->high and high->low.
    3. A few thoughts:
      1. It's not clear to me from the screenshots what the output frequency is, or what the span and center frequency are for the spectrum analyzer. Is the device programmed at this point?
      2. Is the second input AC-coupled to 50Ω? AC-coupling the unused input pin through the 50Ω to GND is required, otherwise it will affect the differential pair biasing.
      3. Are you using an LDO? Could this be the 1/f profile of the power supply leaking onto the output?
      4. Do you have a schematic of the LMX2615 portion of the circuit that you could share? Do you have register programming that you could share?

    Regards,

    Derek Payne

  • Hello Derek,

    Point 1 we need to understand fully

    Point 2 is fully cleared. 

    Point 3.

    a. Start freq = 10 MHz and Stop Freq = 44 GHz, RBW=3 MHz, VBW=10 MHz

    Device is not programmed at this moment. However when we programmed the device this low freq. ( upto 2 to 3 GHz) hump goes. 

    b. second input is terminated with 50 Ohm load and we used LMX2615 EVM schematic for the same. 

    c. We are not using LDO at this stage. But in future we will used TPS7A4501-SP. 

    d. We follow LMX2615 EVM board schematic. For register programming we are using TICS Pro software. file attached for your ref. 50MHz_TCXO_IP_9600_OP.tcs

  • Nilesh,

    Synchronization category for your configuration depends on whether you are using integer mode (and accepting any device-to-device skew that results), or using a higher order MASH value to perform minor phase offset corrections between the devices (and accepting an increase in in-band phase noise and fractional spurs).

    Going through the synchronization chart in Figure 26, we see the following decisions:

    • CHDIV <= 128 (yes, bypassed)
    • OSC_2X=0 (no, doubler enabled)
    • Channel divider is 1,2,4,8 (yes, bypassed)
    • Fout % (2 * Fosc) = 0 (yes, 9600 % (2 * 50) = 0)
    • Integer mode
      • If yes, since CHDIV=1 (bypassed), we're in Category 1 SYNC and we are automatically aligned to the device-to-device skew tolerance of about 60ps max
      • If no (i.e. you want to use the MASH_SEED to adjust the phase of one device relative to another for better alignment), this config cannot be synchronized, because the doubler introduces uncertainty. You'd have to disable the doubler, run the phase detector at 50MHz, and you'd eventually arrive at Category 3 SYNC, requiring a SYNC pulse received on the SYNC pin at the same OSCin cycle on both devices to synchronize them.

    As far as the noise hump you're seeing, I have some settings recommendations that might help:

    • Set FCAL_HPFD_ADJ to the setting for FPD <= 100MHz, this helps filter out high-frequency noise at the PFD and the charge pump
    • Set CAL_CLK_DIV to <= 50MHz, this reduces the state machine clock divider and may help avoid the state machine rattling away at very low frequency, getting mixed into the other supplies like the VCO or the charge pump, etc.
    • Set SEG1_EN=0, this burns extra current and doesn't matter in your config, and may be impacting low frequency noise as a consequence
    • Set MASH_ORDER = 0 (integer) and set PFD_DLY_SEL = 1; even if you ultimately plan to use the MASH_SEED, this can be good for checking the impact of MASH_ORDER on broadband noise.

    Regards,

    Derek Payne