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LMK5B12204: Regarding DPLL and reference input function

Part Number: LMK5B12204
Other Parts Discussed in Thread: LMK05318B

Hello,

I have a quick question about the reference input.

I am testing the tracking or SYNC feature in the LMK05318B EVM with the reference input, but it does not work properly as I expect.

With 96MHz sine wave signal to  PRIREF input  as a reference, I could not get the output frequency shift according to the frequency shift of reference 96MHz.

Can you tell me that my understanding on this is right?

Thank you.

  • Hello, 

    To get synchronization between the input and output, you will need to enable ZDM (zero delay mode).

    Here is the process for enabling ZDM:

    1. Enable the DPLL_ZDM_SYNC_EN bit. The sync phase offset control can be used to align the clocks.

    2. Toggle (on/off) the SYNC_SW bit.

    3. The input and output will now be synced.

    Please note that the input clock must have an integer relationship with the output clock for ZDM to operate properly.

    Regards,

    Kia Rahbar

  • Hello Kia,

    Thank you for the kind explanation, but I think my expression for the question seems to be unclear so let me explain it in more detail.

    I use an 12.8MHz TCXO as an XO input and want to generate some 115.2MHz LVPECL clock outputs. Along with this, I have an external reference clock of 128MHz connected to the PRIREF port. I just want to see and make sure that if the reference clock frequency of 128MHz has changed to like 10Hz up then the clock output of 115.2MHz should be changed to the same direction accordingly. In my setting up the EVM, I can not get the expected result at all and the output is stick to the 115.2MHz regardless of the PRIREF signal.

    Appreciate your kind supports.

  • Hello Kia,

    I think it's better to share TICS configuration screen to you.

    I tried the DCO control on the GPIO pin mode.

    The control itself comes out thru the dedicated GPIO pins, but the frequency of output doesn't change at all.

  • Hello,

    Your understanding is correct and you should be seeing the 10 Hz shift on the output.

    Can you please ensure that your reference is valid and the DPLL is locked?

    The reference is valid if the PRIREF_VALSTAT bit is high. The DPLL is locked if the LOFL_DPLL, LOPL_DPLL, and HLDOVER bits are low.

    Can you also please explain the equipment you are using to measure the output?

    Regards,

    Kia Rahbar

  • Hello Kia,

    When I changed the status read configuration as your guidance, I got the results as I expected.

    I used a spectrum analyzer and vector signal generator in this experiment and I got the frequency shift at the output according to the reference frequency shift.

    Appreciate your supports