CDCE949: Jitter specification

Andreas Nestler

Part Number: CDCE949

Hello, we are using the CDCE949 with the following configuration. External crystal with 20MHz attached to the device, so crystal oscillator is used. VDD is 1.8V (+/-5%) and VDDOUT is 3.3V (+/-5%). The outputs are programmed as follows:

Y1: 40MHz, Y2: 33MHz, Y3: 25MHz, Y4-5 not used, Y6: 20MHz, Y7: 20MHz, Y8, Y9: 12.286MHz (each output). This means the usage of PLL1, 3 and 4 (PLL2 is unused). The critical clock is the 25MHz clock at Y3 with 25MHz.

What maximum jitter (p-p) can we expect at the output Y3 (25MHz)? According datasheet the jitter is specified 180 ps max if 4 PLLs are switching at Vddout=3.3V. If only one PLL is switching (Y2, Y3 outputs used) then the jitter is 100 ps maximum. Why is the jitter dependent from number of PLLs used? Is this caused by device internal crosstalk?

Thanks in advance!

Best regards Andreas N.

over 3 years ago

0 Noel Fung over 3 years ago

TI__Guru** 111720 points

Hi Andreas,

Right, if all the PLLs are using but their output frequencies are not integer multiple of each others, crosstalk exists and as a result, jitter is increased.

0 Andreas Nestler over 3 years ago in reply to Noel Fung

Intellectual 370 points

Hi Noel,

thanks for reply. Could you also state the max. expected jitter for our configuration (using three PLLs with output frequencies as described in my original post). If I check other posts here, TI may be able to deliver the data:

https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/616312/cdce949-which-is-better-between-the-following-two-pll-settings-in-cdce949

Thanks in advance!

BR Andreas N.

0 Noel Fung over 3 years ago in reply to Andreas Nestler

TI__Guru** 111720 points

Hi Andreas,

We cannot estimate the jitter, we don't have a model to predict crosstalk within the device.

Unfortunately, I don't have a board in the lab, I am not able to provide test data for you.

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CDCE949: Jitter specification