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LMK04821: spurious at the internal VCO oscilaantion frequncy

Part Number: LMK04821
Other Parts Discussed in Thread: DAC38RF83

My circuit is as below, DAC38RF83 with LMK04821 -> differential RF amplifier -> balun transformer -> single ended RF output.
The is a spurious on RF output at the LMK04821 internal VCO oscilaantion frequncy, and it is larger than my demand.
Could you give me some advice to suppress this spurious?

LMK04821 in dual loop mode.
CLKIN1: 33.7561MHz
OSCIN: 135.0244MHz (VCXO)
PLL1 R: 256, PLL1 N: 1024
VCOM MUX: VCO1
VCO1 frequency: 2970.5368MHz
VCO1 Divider: 2
PLL2 R: 2, PLL2 N: 11, PLL2 N prescaler: 2
Divided outputs: 67.5122MHz(for FPGA), 135.0244MHz(for DAC reference)


DAC38RF83 clock: 8641.5616MHz(135.0244MHz x4 x16, internal VCO and PLL)

There are spurious of 2970.5368MHz on single ended RF output.
Although I disable the output of DAC38RF83 and all outputs of LMK04821, the spurious level does not change.
The supurious source simply seems to be the LMK04821 VCO oscillation.

  • Hi user6293841,

    Can we see the programming for the LMK04821? Do you have a .tcs file from TICS Pro, or are you using a different software that can produce LMK04821 register programming?

    How are you disabling the outputs? Some methods will work better than others. For instance, just powering down the output format buffers will not be as effective as turning off the device clock path (DCLKoutX_Y_PD).

    Are there nearby outputs which could be disabled, or which could have dividers that are generating parasitics within the same clock group?

    Regards,

    Derek Payne

  • Hi Derek Payne,

    Thank you for your advice. I set bits of CLKout0_1_PD and CLKout2_3_PD and CLKout4_5_PD to '1' to disable divided outputs.

    There are some clock cirucuits, a PLL generating 33.7561MHz reference and a programable VCXO(135.0244MHz). I think these are not the souce of the spurious, because the supurious disappear when I program LMK0481 VCO_PD=1.

    Register dump results;

    0000 00
    0000 00
    0002 00
    0003 06
    0004 50
    0005 5b
    0006 24
    000C 51
    000D 04
    0100 16
    0101 55
    0102 55
    0103 00
    0104 22
    0105 00
    0106 70
    0107 11
    0108 0b
    0109 55
    010A 55
    010B 00
    010C 22
    010D 00
    010E 70
    010F 75
    0110 0b
    0111 55
    0112 55
    0113 00
    0114 02
    0115 00
    0116 71
    0117 01
    0118 18
    0119 55
    011A 55
    011B 00
    011C 02
    011D 00
    011E 79
    011F 33
    0120 08
    0121 55
    0122 55
    0123 00
    0124 02
    0125 00
    0126 79
    0127 00
    0128 08
    0129 55
    012A 55
    012B 00
    012C 02
    012D 00
    012E 79
    012F 00
    0130 06
    0131 55
    0132 55
    0133 00
    0134 02
    0135 00
    0136 79
    0137 33
    0138 20
    0139 03
    013A 00
    013B 58
    013C 00
    013D 08
    013E 03
    013F 00
    0140 08
    0141 00
    0142 00
    0143 11
    0144 7f
    0145 7f
    0146 10
    0147 1b
    0148 02
    0149 42
    014A 02
    014B 02
    014C 00
    014D 00
    014E 40
    014F 7f
    0150 00
    0151 02
    0152 00
    0153 00
    0154 78
    0155 01
    0156 00
    0157 00
    0158 16
    0159 04
    015A 00
    015B d4
    015C 20
    015D 00
    015E 00
    015F 0b
    0160 00
    0161 02
    0162 24
    0163 00
    0164 00
    0165 0c
    0171 aa
    0172 02
    0173 00
    0174 00
    017C 15
    017D 33
    0166 00
    0167 00
    0168 0b
    0169 59
    016A 20
    016B 00
    016C 00
    016D 00
    016E 13
    1FFD 00
    1FFE 00
    1FFF 00

  • Hi user6293841,

    Your loaded configuration file looks good, except first reset the device and then configure all registers. Follow section 9.5.1 mentioned in datasheet for recommended programming sequence.

    Regarding the spurs at VCO frequency, did you able to capture the amplitude at clock output? Ideally with divided output, output buffer have less amplification at VCO frequency as it is already /2 from the VCO itself. There would be expected harmonics of the divided frequency and can have some level at VCO frequency too. Try to powerdown the SYSREF also and see the spur performance.

    Thanks!

    Regards,

    Ajeet Pal

  • Hi Ajeet Pal,

    Thank you for your support. Now I have poor instruments to capture differential signals.
    Just for experiment I disable the output of DAC38RF83 and all divided outputs of LMK04821(clocks and SYSREF for FPGA and DAC, using CLKoutX_Y_PD bits), The level of the spurious at VCO frequency does  not change.

  • Hi,

    What is the spur level you are getting from DAC output? I am still not clear, if any VCO spurs out be there from LMK04821, that anyways can be filtered out through DAC PLL input and not sure, how it is coupled to DAC output.

    There may be possibility, DAC can be generating such frequency internally and seeing on spurs. You can try to change some frequency in DAC and see if it varies?

    Thanks!

    Regards,

    Ajeet Pal

  • Hi Ajeet Pal,

    My sysytem is as below;
    DAC38RF83 with LMK04821 -> differential RF amplifier -> balun transformer -> single ended RF output.
    The spurious is observed at the single ended RF output port.

    When outputs of LMK04821 are disabled and DAC's PLL is free running, DAC internal frequency may change, but level and frequency of the spurious does not change. I think the spurious caused by LMK04821's VCO is coupled to DAC output or amplfier output.

  • Hi,

    It seems, there can be some coupling be present on the board and need to look on the PCB layout, how the LMK04821 and DAC are placed and routing signals.

    To quick verify the VCO coupling thing, I would be suggesting to try the attached configuration, whose VCO frequency change to VCO0, while keeping the other clocks are same. Try this and see, if same VCO spurs seeing in this or not? VCO frequency - 2025.366MHz.

    LMK04821_E2e.tcs

    Apart from this, can you please confirm the both PLLs were locking in your previous setup?

    Thanks!

    Regards,

    Ajeet Pal

  • Thank you for advice. I try the the attached configuration. The spurious levels at the single-ended RF output port are;
    my cofiguration (VCO1 frequency 2970.536MHz)
      2970.536MHz 46dBuV
      2025.366MHz 5dBuV
      1080.195MHz 26dBuV
    the attached configuration (VCO0 frequency 2025.536MHz)
      2970.536MHz 13dBuV
      2025.536MHz 25dBuV
      1080.195MHz 26dBuV
      other frequnecy(0.5~3.3GHz) < 26dBuV,
    In both configurations, both PLL are locking and the frequency of DAC output signal are appropriate.

    Results are nice but I need an explanation for the difference.

  • Hi, 

    In previous configuration, VCO1 was selected (2970.536MHz), which you were seeing higher spurs, may not have proper isolation of VCO1. whereas recent configuration uses VCO0 (2025.366MHz) and generating same required frequencies.

    From the above results, seems VCO1 has less isolation compared to VCO0 and I think you can go ahead with VCO0 configuration.

    Hope, it clarifies your queries.

    Thanks!

    Regards,

    Ajeet Pal