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LMK05028: DPLL Phase Lock Detectors (2)

Part Number: LMK05028

Hi,

I also would like to ask you a question about DPLL Phase Lock Detectors as below.

Following my understanding is correct?

"The Lock ppm and Unlock ppm set here are deviations from the REF TDC Rate [Hz]."

For example, because the input deviation of IN0 is specified as ± 100ppm,

I set "DPLL Phase Lock Detectors"

   Lock ppm: 100ppm

   Unlock ppm: 200ppm

Is there any problem?

My understanding is

    LOFL released at ± 100ppm or less

    LOFL occurs at ± 200ppm or more

Is this correct?

And Also, I have set the default value to "Lock Ave" and "Unlock Ave".

That is to say,

  Lock Ave: 10

 Unlock Ave: 2

However, When DPLL LBW [Hz] is set to 10Hz, Are each Ave value (Lock Ave: 10/ Unlock Ave: 2) valid?

As the datasheet describes following,

"Higher averaging may be useful when locking to an input with high wander or when the DPLL is configured with a narrow loop bandwidth."

Let me ask you this question.

Thanks for your support.

Best Regards,

Takumi

  • Hello Suzuki-san,

    Yes, your lock ppm and unlock ppm understanding is correct.

    1. Lock ppm:
      1. The DPLL is considered to be frequency locked if the frequency error between the VCO1 and the references is within the lock threshold in ppm.
      2. If you have a reference input with a large ppm, you will want to increase the Lock ppm.
      3. For your settingsc, LOFL released at ± 100ppm or less.
    2. Unlock ppm:
      1. While the DPLL is frequency locked, it's considered to be frequency unlocked if the frequency error exceeds the unlock threshold in ppm.
      2. The unlock ppm should be greater than the lock ppm.
      3. For your settings, LOFL occurs at ± 200ppm or more.
    3. Lock avg and unlock avg:
      1. Higher values allow for an input clock with a dithered frequency. The default settings of 10 and 2 are suitable for most applications.

    Regards,

    Kia Rahbar

  • Hi Kia-san,

    Thank you for your support !

    Regards,

    Takumi