Hi TI team
Let me ask with you about initial setting of GPIO for LOL.
We are using the GPIO5 as LOL (Los of Lock) signal to control (reset) the external device (FPGA).
Until now, we have set the GPIO5 setting as follows.
# we are using only DPLL2 (do not use DPLL1)
R16(Adress=10h)=00h : no mask
R17(Adress=11h)=00h : no mask
R18(Adress=12h)=00h : no mask
R25(Adress=19h)=00h : disable interrupt
R48(Adress=30h)=70h : GPIO5 = DPLL2 Loss of Lock
R184(Adress=B8h)=F4h : GPIO5 polarity = Active Low
However, we faced the following issue with the above setting.
Issue :
GPIO5 becomes High after DPLL2 frequency locks
(at this time phase lock has not yet been done).
It couse an issue in the initialization of the external device.
So, we would like to modify the GPIO5 setting to assert when frequency lock and phase lock of DPLL2 has done.
Following is the modified setting of GPIO5.
R16(Adress=10h)=37h : APLL2 : no mask , other : mask
R17(Adress=11h)=FFh : all mask
R18(Adress=12h)=3Fh : DPLL2 Phase-Lock, Freq-Lock : no mask , other:mask
R25(Adress=19h)=03h : Interrupt enable / Interrupt logical AND
R48(Adress=30h)=0Ah : GPIO5 = Interupt
R184(Adress=B8h)=F0h : GPIO5 polarity = Active High
In our evaluation, it works as we expected.
If you have any concern, please let us know about it.
Best Regards
Toshiaki Kondo
