LMK04828: SYSREF Continuous Mode

Omelio Barba

Part Number: LMK04828

Hi, TI.

We are trying to get the followings outputs with the LMK04828 in Nested Zero-Delay Dual-Loop Mode.

SDCLKout3: 625 MHz (DCLK)
SDCLKout5: 10 MHz (SYSREF)
DCLKout6: 250 MHz (DCLK)
SDCLKout9: 10 MHz (SYSREF)

SDCLKout3 and DCLKout6 outputs configured as device clocks (DCLK) are working properly (checked on lab). On the other hand, we are not getting any output on SDCLKout5 and SDCLKout9 outputs, configured as SYSREF clocks.

We are using continuous SYSREF mode.

Attached is the configuration sequence we are using and a simplified LMK04828 block diagram.

Please, can you take a look to the configuration and give us some advice about what we might be doing wrong?

Regards,

/***********************************/
/* 10M-250M-650M-RYT-v1.0.1 */
/***********************************/

/********************/
/* System functions */
/********************/

0x0000 0x80 // Soft reset, 3-wire mode enabled (default)
0x0002 0x00

/*****************************************************************/
/* Device Clock and SYSREF Clock Output Controls (0x100 - 0x137) */
/*****************************************************************/

// DCLKout0 and SDCLKout1
0x0100 0x02 // DCLK Divider: 2; Input/Output Drive Level Off;
0x0101 0x55
0x0103 0x00
0x0104 0x00 // SDCLK Source: DCLK;
0x0105 0x00
0x0106 0xFB // Group Powerdown: On;  Powerdown SDCLK: On;
0x0107 0x00 // SDCLK Format: Powerdown; DCLK Format: Powerdown;

// DCLKout2 and SDCLKout3
0x0108 0x04 // DCLK Divider: 4; Input/Output Drive Level Off;
0x0109 0x55
0x010B 0x00 
0x010C 0x00 // SDCLK Source: DCLK;
0x010D 0x00
0x010E 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x010F 0x10 // SDCLK Format: LVDS; DCLK Format: Powerdown;

// DCLKout4 and SDCLKout5
0x0110 0x08 // DCLK Divider: 4; Input/Output Drive Level Off;
0x0111 0x55
0x0113 0x00
0x0114 0x20 // SDCLK Source: SYSREF;
0x0115 0x00
0x0116 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x0117 0x10 // SDCLK Format: LVDS; DCLK Format: Powerdown;

// DCLKout6 and SDCLKout7
0x0118 0x0A // DCLK Divider: 10; Input/Output Drive Level Off;
0x0119 0x55
0x011B 0x00
0x011C 0x00 // SDCLK Source: DCLK;
0x011D 0x00
0x011E 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x011F 0x01 // SDCLK Format: Powerdown; DCLK Format: LVDS;

// DCLKout8 and SDCLKout9
0x0120 0x08 // DCLK Divider: 8; Input/Output Drive Level Off;
0x0121 0x55
0x0123 0x00
0x0124 0x20 // SDCLK Source: SYSREF;
0x0125 0x00
0x0126 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x0127 0x10 // SDCLK Format: LVDS; DCLK Format: Powerdown;

// DCLKout10 and SDCLKout11
0x0128 0x08 // DCLK Divider: 8; Input/Output Drive Level Off;
0x0129 0x55
0x012B 0x00
0x012C 0x00 // SDCLK Source: DCLK;
0x012D 0x00
0x012E 0xFB // Group Powerdown: On;  Powerdown SDCLK: On;
0x012F 0x00 // SDCLK Format: Powerdown; DCLK Format: Powerdown;

// DCLKout12 and SDCLKout13
0x0130 0x02 // DCLK Divider: 2; Input/Output Drive Level Off;
0x0131 0x55
0x0133 0x00
0x0134 0x00 // SDCLK Source: DCLK;
0x0135 0x00
0x0136 0xFB // Group Powerdown: On;  Powerdown SDCLK: On;
0x0137 0x00 // SDCLK Format: Powerdown; DCLK Format: Powerdown;

/**************************************************/
/* SYSREF, SYNC and Device Config (0x138 - 0x145) */
/**************************************************/
 
0x0138 0x00 // OSCout Format: Powerdown (CLKin2); PLL2 VCO: VCO_0 ;
0x0139 0x00 // SYSREF_MUX = 0 (Normal SYNC)
0x013A 0x00 // SYSREF Divider High: 0
0x013B 0xFA // SYSREF Divider Low: 0xFA=250 (2500MHz/250=10 MHz)
0x013C 0x00
0x013D 0x00
0x013E 0x03 // SYSREF Pulse count: 8 pulses
0x013F 0x09 // Feedback Mux: Enabled; Feedback Mux Source: DCLKout6; PLL1 N Mux Source: Feedback Mux
0x0140 0x01 // SYSREF Global Powrdown Bit: Off ; SYSREF Powerdown: Off;  SYSREF DDLY Powerdown: Off; SYSREF Pulse Generator Powerdown: On
0x0141 0x00
0x0142 0x00
0x0143 0x11 // SYNC_MODE = 1: SYNC event generated from SYNC pin, SYNC_POL = 0
0x0144 0x00 // Able SYSREF divider and clocks dividers from becoming synchronized during a SYNC event.
0x0145 0x7F // Fixed Register: Always write 0x7F (127).

/*********************************/
/* CLKin Control (0x146 - 0x149) */
/*********************************/

0x0146 0x28 // CLKin0 and CLKin2 enabled to be used dring auto-switching; CLKin0/1/2_TYPE = Bipolar;
0x0147 0x2A // CLKin0_OUT_MUX = 0x02 (PLL1); CLKin1_OUT_MUX = 0x02 (PLL1); CLKin_SEL_MODE = 0x02 (CLKin2 Manual);
0x0148 0x02 // Configure CLKin_SEL0 as an input (with pull down);
0x0149 0x42 // Configure CLKin_SEL1 as an input (with pull down); SDIO pin is open drain during SPI readback in 3 wire mode;

/****************************/
/* RESET_MUX and RESET_TYPE */
/****************************/

0x014A 0x02 // Configure RESET pin as an input.

/****************************/
/* Holdover (0x14B - 0x152) */
/****************************/

0x014B 0x02 // LOS_EN = '0'; TRACK_EN = '0'; MAN_DAC_EN = '0'; MAN_DAC = 512;
0x014C 0x00 //
0x014D 0x00 //
0x014E 0xC0 // DAC_CLK_MULT = 0x03 (16384); DAC_CLK_MULT = 0x00 (4);
0x014F 0x7F // DAC_CLK_CNTR = 127;
0x0150 0x00 // HOLDOVER_EN = '0'; HOLDOVER_HITLESS_SWITCH = '0'
0x0151 0x02 // HOLDOVER_DLD_CNT = 512
0x0152 0x00 // HOLDOVER_DLD_CNT = 512

/**************************************/
/* PLL1 Configuration (0x153 - 0x15F) */
/**************************************/

0x0153 0x00 // CLKin0_R = 2
0x0154 0x02 // CLKin0_R = 2
0x0155 0x00 // CLKin1_R = 120
0x0156 0x78 // CLKin1_R = 120
0x0157 0x00 // CLKin2_R = 2
0x0158 0x02 // CLKin2_R = 2
0x0159 0x00 // PLL1_N(13:0) = 50
0x015A 0x32 // PLL1_N(13:0) = 50
0x015B 0xD4 // CP Gain=0x04(450uA); PLL1 CPout1: Active (Not TRI-STATED); PLL1_WND_SIZE=0x03(43ns)
0x015C 0x20 // PLL1_DLD_CNT = 8192;
0x015D 0x00 // PLL1_DLD_CNT = 8192;
0x015E 0x00 // 
0x015F 0x0B // Status_LD1. PLL1_LD_TYPE = 0x03 (Output (push-pull)); PLL1_LD_MUX = 0x01 (PLL1 DLD);               

/**************************************/
/* PLL2 Configuration (0x160 - 0x165) */
/**************************************/

0x0160 0x00 // PLL2_R = 10
0x0161 0x0A // PLL2_R = 10
0x0162 0x44 // 0x44 -> Freq Doubler: Disabled; OSCin FREQ 67MHz-127MHz; PLL2_P = 2;
0x0163 0x00 
0x0164 0x00 // PLL2_N_CAL = 25 
0x0165 0x19 // PLL2_N_CAL = 25	

// Fixed registers
0x0171 0xAA // Program register 0x171 to 0xAA
0x0172 0x02 // Program register 0x172 to 0x02

// Programming registers 0x17C and 0x17D
0x017C 0x15 // OPT_REG_1. 24 for LMK04826; 21 for LMK04828 and LMK04821"  
0x017D 0x33 // OPT_REG_2. 119 for LMK04826; 51 for LMK04828 and LMK04821"	

/**************************************/
/* PLL2 Configuration (0x166 - 0x16E) */
/**************************************/

0x0166 0x00 // PLL2_N(17:0) = 100
0x0167 0x00 // PLL2_N(17:0) = 100
0x0168 0x64 // PLL2_N(17:0) = 100
0x0169 0x59
0x016A 0x20
0x016B 0x00
0x016C 0x00
0x016D 0x00
0x016E 0x13 // Status_LD2. PLL2_LD_TYPE = 0x03 (Output (push-pull)); PLL2_LD_MUX = 0x02 (PLL2 DLD);

/***************************************************/
/* Sync Dividers Sequence and SYSREF Configuration */
/***************************************************/

// Configure sync ciruit to sync dividers:
0x0139 0x00 // SYSREF_CLKin0_MUX=0b, SYSREF_MUX=0d (Normal SYNC)
0x0143 0x11 // SYNC_EN=1b and SYNC_MODE=1d SYNC event generated from SYNC pin
0x0144 0x00 // Configure SYSREF and Device clock to be synchronized during a SYNC event

// Generate a SYNC event
0x0143 0x31 // Toggle SYNC_POL to generate a SYNC event
0x0143 0x11 // Toggle SYNC_POL to generate a SYNC event

// Set user desired SYSREF configuration
0x0144 0xFF // Avoid dividers to be synced by SYNC Pin
0x0143 0x00 // Prevents SYNC pin from generating a SYNC event.
0x0139 0x03 // SYSREF_MUX=3d (SYSREF continouos)

lmk04828-block-diagram.pdf

over 3 years ago

0 Derek Payne over 3 years ago

TI__Mastermind 34270 points

Hello Omelio,

SYSREF_DDLY cannot be zero - please set this to a minimum of 8.

Other general comments:

I see that your PLL2 phase detector frequency is 12.5 MHz. Unless your VCXO is very noisy, I would recommend setting the phase detector frequency to 125 MHz as this will improve in-band performance by around 10 dB (though loop bandwidth will also increase). You could try checking the differences in PLLatinum Sim.
It looks like you set the N-Cal divider assuming that the N-Cal divide value is interacting with the frequency coming from FB_MUX. This is incorrect. When the LSBs of the PLL2 N-divider register (0x168) are written, a calibration event is triggered for PLL2. The calibration event swaps the current N-divider value with the one in the N-Cal divider registers, then uses the prescaler feedback path to calibrate the VCO. In other words, if you're using prescaler path for feedback on PLL2 at all times, you should set N-Cal divider equal to N-divider. Otherwise, if you intended to use the FB_MUX feedback to PLL2, you would set N-Cal divider to 100, and N-divider to 250/PLL2_PFD.

Regards,

Derek Payne

0 Omelio Barba over 3 years ago in reply to Derek Payne

Prodigy 10 points

Hello Derek.

Thanks for the very detailed answer.

We already fixed the SYSREF_DDLY from 0 to 8 (minimun) as you said.
We were not aware of the PLL2 calibration routine. Thanks for the detailed description. In fact, we are using prescaler path for feedback PLL2 at all times. We will take your suggestion to set N-Cal divider equal to N-divider (equal to 100).
About PLL2 PDF of 12.5MHz or 125MHz we are going to do further analysis using PLLatinum Sim.

We will make some tests on lab with the new configuration and I'll get back to you with updates.

I hope this resolves our issues.

Thanks again,

Omelio

Pd. New configuration and block diagram attached.

8666.lmk04828-block-diagram.pdf

/***********************************/
/* 10M-250M-650M-v1.0.2 */
/***********************************/

/********************/
/* System functions */
/********************/

0x0000 0x80 // Soft reset, 3-wire mode enabled (default)
0x0002 0x00

/*****************************************************************/
/* Device Clock and SYSREF Clock Output Controls (0x100 - 0x137) */
/*****************************************************************/

// DCLKout0 and SDCLKout1
0x0100 0x02 // DCLK Divider: 2; Input/Output Drive Level Off;
0x0101 0x55
0x0103 0x00
0x0104 0x00 // SDCLK Source: DCLK;
0x0105 0x00
0x0106 0xFB // Group Powerdown: On;  Powerdown SDCLK: On;
0x0107 0x00 // SDCLK Format: Powerdown; DCLK Format: Powerdown;

// DCLKout2 and SDCLKout3
0x0108 0x04 // DCLK Divider: 4; Input/Output Drive Level Off;
0x0109 0x55
0x010B 0x00 
0x010C 0x00 // SDCLK Source: DCLK;
0x010D 0x00
0x010E 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x010F 0x10 // SDCLK Format: LVDS; DCLK Format: Powerdown;

// DCLKout4 and SDCLKout5
0x0110 0x08 // DCLK Divider: 4; Input/Output Drive Level Off;
0x0111 0x55
0x0113 0x00
0x0114 0x20 // SDCLK Source: SYSREF;
0x0115 0x00
0x0116 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x0117 0x10 // SDCLK Format: LVDS; DCLK Format: Powerdown;

// DCLKout6 and SDCLKout7
0x0118 0x0A // DCLK Divider: 10; Input/Output Drive Level Off;
0x0119 0x55
0x011B 0x00
0x011C 0x00 // SDCLK Source: DCLK;
0x011D 0x00
0x011E 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x011F 0x01 // SDCLK Format: Powerdown; DCLK Format: LVDS;

// DCLKout8 and SDCLKout9
0x0120 0x08 // DCLK Divider: 8; Input/Output Drive Level Off;
0x0121 0x55
0x0123 0x00
0x0124 0x20 // SDCLK Source: SYSREF;
0x0125 0x00
0x0126 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x0127 0x10 // SDCLK Format: LVDS; DCLK Format: Powerdown;

// DCLKout10 and SDCLKout11
0x0128 0x08 // DCLK Divider: 8; Input/Output Drive Level Off;
0x0129 0x55
0x012B 0x00
0x012C 0x00 // SDCLK Source: DCLK;
0x012D 0x00
0x012E 0xFB // Group Powerdown: On;  Powerdown SDCLK: On;
0x012F 0x00 // SDCLK Format: Powerdown; DCLK Format: Powerdown;

// DCLKout12 and SDCLKout13
0x0130 0x02 // DCLK Divider: 2; Input/Output Drive Level Off;
0x0131 0x55
0x0133 0x00
0x0134 0x00 // SDCLK Source: DCLK;
0x0135 0x00
0x0136 0xFB // Group Powerdown: On;  Powerdown SDCLK: On;
0x0137 0x00 // SDCLK Format: Powerdown; DCLK Format: Powerdown;

/**************************************************/
/* SYSREF, SYNC and Device Config (0x138 - 0x145) */
/**************************************************/
 
0x0138 0x00 // OSCout Format: Powerdown (CLKin2); PLL2 VCO: VCO_0 ;
0x0139 0x00 // SYSREF_MUX = 0 (Normal SYNC)
0x013A 0x00 // SYSREF Divider High: 0
0x013B 0xFA // SYSREF Divider Low: 0xFA=250 (2500MHz/250=10 MHz)
0x013C 0x00 // SYSREF Digital Delay (SYSREF_DDLY = 8)
0x013D 0x08 // SYSREF Digital Delay (SYSREF_DDLY = 8)
0x013E 0x03 // SYSREF Pulse count: 8 pulses
0x013F 0x09 // Feedback Mux: Enabled; Feedback Mux Source: DCLKout6; PLL1 N Mux Source: Feedback Mux
0x0140 0x01 // SYSREF Global Powrdown Bit: Off ; SYSREF Powerdown: Off;  SYSREF DDLY Powerdown: Off; SYSREF Pulse Generator Powerdown: On
0x0141 0x00
0x0142 0x00
0x0143 0x11 // SYNC_MODE = 1: SYNC event generated from SYNC pin, SYNC_POL = 0
0x0144 0x00 // Able SYSREF divider and clocks dividers from becoming synchronized during a SYNC event.
0x0145 0x7F // Fixed Register: Always write 0x7F (127).

/*********************************/
/* CLKin Control (0x146 - 0x149) */
/*********************************/

0x0146 0x28 // CLKin0 and CLKin2 enabled to be used dring auto-switching; CLKin0/1/2_TYPE = Bipolar;
0x0147 0x2A // CLKin0_OUT_MUX = 0x02 (PLL1); CLKin1_OUT_MUX = 0x02 (PLL1); CLKin_SEL_MODE = 0x02 (CLKin2 Manual);
0x0148 0x02 // Configure CLKin_SEL0 as an input (with pull down);
0x0149 0x42 // Configure CLKin_SEL1 as an input (with pull down); SDIO pin is open drain during SPI readback in 3 wire mode;

/****************************/
/* RESET_MUX and RESET_TYPE */
/****************************/

0x014A 0x02 // Configure RESET pin as an input.

/****************************/
/* Holdover (0x14B - 0x152) */
/****************************/

0x014B 0x02 // LOS_EN = '0'; TRACK_EN = '0'; MAN_DAC_EN = '0'; MAN_DAC = 512;
0x014C 0x00 //
0x014D 0x00 //
0x014E 0xC0 // DAC_CLK_MULT = 0x03 (16384); DAC_CLK_MULT = 0x00 (4);
0x014F 0x7F // DAC_CLK_CNTR = 127;
0x0150 0x00 // HOLDOVER_EN = '0'; HOLDOVER_HITLESS_SWITCH = '0'
0x0151 0x02 // HOLDOVER_DLD_CNT = 512
0x0152 0x00 // HOLDOVER_DLD_CNT = 512

/**************************************/
/* PLL1 Configuration (0x153 - 0x15F) */
/**************************************/

0x0153 0x00 // CLKin0_R = 2
0x0154 0x02 // CLKin0_R = 2
0x0155 0x00 // CLKin1_R = 120
0x0156 0x78 // CLKin1_R = 120
0x0157 0x00 // CLKin2_R = 2
0x0158 0x02 // CLKin2_R = 2
0x0159 0x00 // PLL1_N(13:0) = 50
0x015A 0x32 // PLL1_N(13:0) = 50
0x015B 0xD4 // CP Gain=0x04(450uA); PLL1 CPout1: Active (Not TRI-STATED); PLL1_WND_SIZE=0x03(43ns)
0x015C 0x20 // PLL1_DLD_CNT = 8192;
0x015D 0x00 // PLL1_DLD_CNT = 8192;
0x015E 0x00 // 
0x015F 0x0B // Status_LD1. PLL1_LD_TYPE = 0x03 (Output (push-pull)); PLL1_LD_MUX = 0x01 (PLL1 DLD);               

/**************************************/
/* PLL2 Configuration (0x160 - 0x165) */
/**************************************/

0x0160 0x00 // PLL2_R = 10
0x0161 0x0A // PLL2_R = 10
0x0162 0x44 // 0x44 -> Freq Doubler: Disabled; OSCin FREQ 67MHz-127MHz; PLL2_P = 2;
0x0163 0x00 
0x0164 0x00 // PLL2_N_CAL = 100 
0x0165 0x64 // PLL2_N_CAL = 100	

// Fixed registers
0x0171 0xAA // Program register 0x171 to 0xAA
0x0172 0x02 // Program register 0x172 to 0x02

// Programming registers 0x17C and 0x17D
0x017C 0x15 // OPT_REG_1. 24 for LMK04826; 21 for LMK04828 and LMK04821"  
0x017D 0x33 // OPT_REG_2. 119 for LMK04826; 51 for LMK04828 and LMK04821"	

/**************************************/
/* PLL2 Configuration (0x166 - 0x16E) */
/**************************************/

0x0166 0x00 // PLL2_N(17:0) = 100
0x0167 0x00 // PLL2_N(17:0) = 100
0x0168 0x64 // PLL2_N(17:0) = 100
0x0169 0x59
0x016A 0x20
0x016B 0x00
0x016C 0x00
0x016D 0x00
0x016E 0x13 // Status_LD2. PLL2_LD_TYPE = 0x03 (Output (push-pull)); PLL2_LD_MUX = 0x02 (PLL2 DLD);

/***************************************************/
/* Sync Dividers Sequence and SYSREF Configuration */
/***************************************************/

// Configure sync ciruit to sync dividers:
0x0139 0x00 // SYSREF_CLKin0_MUX=0b, SYSREF_MUX=0d (Normal SYNC)
0x0143 0x11 // SYNC_EN=1b and SYNC_MODE=1d SYNC event generated from SYNC pin
0x0144 0x00 // Configure SYSREF and Device clock to be synchronized during a SYNC event

// Generate a SYNC event
0x0143 0x31 // Toggle SYNC_POL to generate a SYNC event
0x0143 0x11 // Toggle SYNC_POL to generate a SYNC event

// Set user desired SYSREF configuration
0x0144 0xFF // Avoid dividers to be synced by SYNC Pin
0x0143 0x00 // Prevents SYNC pin from generating a SYNC event.
0x0139 0x03 // SYSREF_MUX=3d (SYSREF continuos)

0 Omelio Barba over 3 years ago in reply to Omelio Barba

Prodigy 10 points

Hi Derek,

In addition to the changes you proposed we had to make the following modifications to get SDCLK outputs working properly as SYSREF Continuous clocks:

Before:

- Line 105: 0x0149 0x42 // Configure CLKin_SEL1 as an input (with pull down); SDIO pin is open drain during SPI readback in 3 wire mode;
- Line 194: 0x0143 0x00 // SYNC functionality disable. Prevents SYNC pin from generating a SYNC event.

After:

- Línea 105: 0x149 0x02 // Configure CLKin_SEL1 as an input (with pull down); SDIO pin in push-pull during SPI readback, in 3 wire mode;
- Línea 192: 0x0143 0x10 // SYNC functionality enable. Prevents SYNC pin from generating a SYNC event.

Thank you very much,

Omelio.

/***********************************/
/* HexReg-10M-250M-625M-v1.0.3 */
/***********************************/

/********************/
/* System functions */
/********************/

0x0000 0x80 // Soft reset, 3-wire mode enabled (default)
0x0002 0x00

/*****************************************************************/
/* Device Clock and SYSREF Clock Output Controls (0x100 - 0x137) */
/*****************************************************************/

// DCLKout0 and SDCLKout1
0x0100 0x02 // DCLK Divider: 2; Input/Output Drive Level Off;
0x0101 0x55
0x0103 0x00
0x0104 0x00 // SDCLK Source: DCLK;
0x0105 0x00
0x0106 0xFB // Group Powerdown: On;  Powerdown SDCLK: On;
0x0107 0x00 // SDCLK Format: Powerdown; DCLK Format: Powerdown;

// DCLKout2 and SDCLKout3
0x0108 0x04 // DCLK Divider: 4; Input/Output Drive Level Off;
0x0109 0x55
0x010B 0x00 
0x010C 0x00 // SDCLK Source: DCLK;
0x010D 0x00
0x010E 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x010F 0x10 // SDCLK Format: LVDS; DCLK Format: Powerdown;

// DCLKout4 and SDCLKout5
0x0110 0x08 // DCLK Divider: 4; Input/Output Drive Level Off;
0x0111 0x55
0x0113 0x00
0x0114 0x20 // SDCLK Source: SYSREF;
0x0115 0x00
0x0116 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x0117 0x10 // SDCLK Format: LVDS; DCLK Format: Powerdown;

// DCLKout6 and SDCLKout7
0x0118 0x0A // DCLK Divider: 10; Input/Output Drive Level Off;
0x0119 0x55
0x011B 0x00
0x011C 0x00 // SDCLK Source: DCLK;
0x011D 0x00
0x011E 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x011F 0x01 // SDCLK Format: Powerdown; DCLK Format: LVDS;

// DCLKout8 and SDCLKout9
0x0120 0x08 // DCLK Divider: 8; Input/Output Drive Level Off;
0x0121 0x55
0x0123 0x00
0x0124 0x20 // SDCLK Source: SYSREF;
0x0125 0x00
0x0126 0xF2 // Group Powerdown: Off;  Powerdown SDCLK: Off;
0x0127 0x10 // SDCLK Format: LVDS; DCLK Format: Powerdown;

// DCLKout10 and SDCLKout11
0x0128 0x08 // DCLK Divider: 8; Input/Output Drive Level Off;
0x0129 0x55
0x012B 0x00
0x012C 0x00 // SDCLK Source: DCLK;
0x012D 0x00
0x012E 0xFB // Group Powerdown: On;  Powerdown SDCLK: On;
0x012F 0x00 // SDCLK Format: Powerdown; DCLK Format: Powerdown;

// DCLKout12 and SDCLKout13
0x0130 0x02 // DCLK Divider: 2; Input/Output Drive Level Off;
0x0131 0x55
0x0133 0x00
0x0134 0x00 // SDCLK Source: DCLK;
0x0135 0x00
0x0136 0xFB // Group Powerdown: On;  Powerdown SDCLK: On;
0x0137 0x00 // SDCLK Format: Powerdown; DCLK Format: Powerdown;

/**************************************************/
/* SYSREF, SYNC and Device Config (0x138 - 0x145) */
/**************************************************/
 
0x0138 0x00 // OSCout Format: Powerdown (CLKin2); PLL2 VCO: VCO_0 ;
0x0139 0x00 // SYSREF_MUX = 0 (Normal SYNC)
0x013A 0x00 // SYSREF Divider High: 0
0x013B 0xFA // SYSREF Divider Low: 0xFA=250 (2500MHz/250=10 MHz)
0x013C 0x00 // SYSREF Digital Delay (SYSREF_DDLY = 8)
0x013D 0x08 // SYSREF Digital Delay (SYSREF_DDLY = 8)
0x013E 0x03 // SYSREF Pulse count: 8 pulses
0x013F 0x09 // Feedback Mux: Enabled; Feedback Mux Source: DCLKout6; PLL1 N Mux Source: Feedback Mux
0x0140 0x01 // SYSREF Global Powrdown Bit: Off ; SYSREF Powerdown: Off;  SYSREF DDLY Powerdown: Off; SYSREF Pulse Generator Powerdown: On
0x0141 0x00
0x0142 0x00
0x0143 0x11 // SYNC_MODE = 1: SYNC event generated from SYNC pin, SYNC_POL = 0
0x0144 0x00 // Able SYSREF divider and clocks dividers from becoming synchronized during a SYNC event.
0x0145 0x7F // Fixed Register: Always write 0x7F (127).

/*********************************/
/* CLKin Control (0x146 - 0x149) */
/*********************************/

0x0146 0x28 // CLKin0 and CLKin2 enabled to be used dring auto-switching; CLKin0/1/2_TYPE = Bipolar;
0x0147 0x2A // CLKin0_OUT_MUX = 0x02 (PLL1); CLKin1_OUT_MUX = 0x02 (PLL1); CLKin_SEL_MODE = 0x02 (CLKin2 Manual);
0x0148 0x02 // Configure CLKin_SEL0 as an input (with pull down);
0x0149 0x02 // Configure CLKin_SEL1 as an input (with pull down); SDIO pin in push-pull during SPI readback, in 3 wire mode;

/****************************/
/* RESET_MUX and RESET_TYPE */
/****************************/

0x014A 0x02 // Configure RESET pin as an input.

/****************************/
/* Holdover (0x14B - 0x152) */
/****************************/

0x014B 0x02 // LOS_EN = '0'; TRACK_EN = '0'; MAN_DAC_EN = '0'; MAN_DAC = 512;
0x014C 0x00 //
0x014D 0x00 //
0x014E 0xC0 // DAC_CLK_MULT = 0x03 (16384); DAC_CLK_MULT = 0x00 (4);
0x014F 0x7F // DAC_CLK_CNTR = 127;
0x0150 0x00 // HOLDOVER_EN = '0'; HOLDOVER_HITLESS_SWITCH = '0'
0x0151 0x02 // HOLDOVER_DLD_CNT = 512
0x0152 0x00 // HOLDOVER_DLD_CNT = 512

/**************************************/
/* PLL1 Configuration (0x153 - 0x15F) */
/**************************************/

0x0153 0x00 // CLKin0_R = 2
0x0154 0x02 // CLKin0_R = 2
0x0155 0x00 // CLKin1_R = 120
0x0156 0x78 // CLKin1_R = 120
0x0157 0x00 // CLKin2_R = 2
0x0158 0x02 // CLKin2_R = 2
0x0159 0x00 // PLL1_N(13:0) = 50
0x015A 0x32 // PLL1_N(13:0) = 50
0x015B 0xD4 // CP Gain=0x04(450uA); PLL1 CPout1: Active (Not TRI-STATED); PLL1_WND_SIZE=0x03(43ns)
0x015C 0x20 // PLL1_DLD_CNT = 8192;
0x015D 0x00 // PLL1_DLD_CNT = 8192;
0x015E 0x00 // 
0x015F 0x0B // Status_LD1. PLL1_LD_TYPE = 0x03 (Output (push-pull)); PLL1_LD_MUX = 0x01 (PLL1 DLD);               

/**************************************/
/* PLL2 Configuration (0x160 - 0x165) */
/**************************************/

0x0160 0x00 // PLL2_R = 10
0x0161 0x0A // PLL2_R = 10
0x0162 0x44 // 0x44 -> Freq Doubler: Disabled; OSCin FREQ 67MHz-127MHz; PLL2_P = 2;
0x0163 0x00 
0x0164 0x00 // PLL2_N_CAL = 100 
0x0165 0x64 // PLL2_N_CAL = 100	

// Fixed registers
0x0171 0xAA // Program register 0x171 to 0xAA
0x0172 0x02 // Program register 0x172 to 0x02

// Programming registers 0x17C and 0x17D
0x017C 0x15 // OPT_REG_1. 24 for LMK04826; 21 for LMK04828 and LMK04821"  
0x017D 0x33 // OPT_REG_2. 119 for LMK04826; 51 for LMK04828 and LMK04821"	

/**************************************/
/* PLL2 Configuration (0x166 - 0x16E) */
/**************************************/

0x0166 0x00 // PLL2_N(17:0) = 100
0x0167 0x00 // PLL2_N(17:0) = 100
0x0168 0x64 // PLL2_N(17:0) = 100
0x0169 0x59
0x016A 0x20
0x016B 0x00
0x016C 0x00
0x016D 0x00
0x016E 0x13 // Status_LD2. PLL2_LD_TYPE = 0x03 (Output (push-pull)); PLL2_LD_MUX = 0x02 (PLL2 DLD);

/***************************************************/
/* Sync Dividers Sequence and SYSREF Configuration */
/***************************************************/

// Configure sync ciruit to sync dividers:
0x0139 0x00 // SYSREF_CLKin0_MUX=0b, SYSREF_MUX=0d (Normal SYNC)
0x0143 0x11 // SYNC_EN=1b and SYNC_MODE=1d SYNC event generated from SYNC pin
0x0144 0x00 // Configure SYSREF and Device clock to be synchronized during a SYNC event

// Generate a SYNC event
0x0143 0x31 // Toggle SYNC_POL to generate a SYNC event
0x0143 0x11 // Toggle SYNC_POL to generate a SYNC event

// Set user desired SYSREF configuration
0x0144 0xFF // Avoid dividers to be synced by SYNC Pin
0x0143 0x10 // SYNC functionality enable. Prevents SYNC pin from generating a SYNC event.
0x0139 0x03 // SYSREF_MUX=3d (SYSREF continuos)

Clock & timing

Clock & timing forum

LMK04828: SYSREF Continuous Mode