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LMX2820: PLL lock issue

Kiran Kumar R
Intellectual 265 points
Part Number: LMX2820
Other Parts Discussed in Thread: LMK04832

Hi Team,

We are using  LMK04832 and LMX2820 is our boards and we are facing PLL locking issue in LMX2820. The below image shows the clock architecture.

PFA the schematics of LMK04832 and LMX2820 of our design. And also find the attached LMK04832 and LMX2820 .tcs file

LMK04832 AND LMX2820 DESIGN.pdf

ADC_LMX2820_FPD_270MHz_2700output.tcs

DAC_LMX2820_FPD_270MHz_5400output.tcs

MS_LRDE_WBRFU_LMK04832_RF_Clock_clkin1.tcs

As per this design, We are not facing any issue and the LMK and LMX PLLs are locking properly. 

We wanted to change the frequencies and hence we made required hardware changes and after that the LMX2820 PLL is not locking. PFA the .zip file for schematic of LMK04832 and LMX2820 for new frequency with loop filter and VCXO updated and also find the .tcs files and pllatinum sim file (Loop filters calculation).

LMK04832 and LMX2820 new frequency.zip

We have 6 boards and the hardware changes for new frequency is done on one board in that, CPOUT pin of LMX2820 measures 0 Volts. where as in other boards it measures 1.3 to 1.4 Volts (old frequency design) 

what can be the cause for LMX2820 PLL not locking for the new frequency changes?

--

Regards

Kiran 

  • 0
    TI__Guru** 107260 points

    Hi Kiran,

    How about the LMK device that is associated with the unlock LMX2820? Did that LMK device provide a healthy 320MHz clock to LMX2820? Register configuration and loop filter of LMx2820 is fine. Could you confirm this is not a programming issue?

  • 0 in reply to Noel Fung
    Intellectual 265 points

    Hi Noel,

    The LMK looks fine as its both PLL is locking and we are using its other clock outputs which are going to FPGA. 

    To debug this we tried to program the LMK04832 on other board (where hardware changes not done and LMK has 120MHz VCXO) in single loop mode to generate 320MHz to LMX. In this method, the LMK04832 PLL is locking (without changes in loop filter values), but LMX2820 PLL is not locking where it locks for initial designed frequency. (might be because we have not changed loop filter values for new design). 

    Thinking 320MHz from LMK04832 may have some noise considering it has little higher frequency we tried generating 160MHz from LMK04832 which is going to LMX and modified LMX program for 160MHz input. Even in this method LMX was not locking. 

    Noel Fung said:
    Could you confirm this is not a programming issue?

    We have not probed the SPI lines because this was working fine in earlier design. I will check it and confirm. 

    --

    Regards,

    Kiran

  • 0 in reply to Kiran Kumar R
    Intellectual 265 points

    Hi Noel,

    We tried changing the hardware in one more board and we are observing the same behavior. Can you please check and confirm the loops filters values for LMX are proper.?  The voltage level on CPOUT pin is slowly changing between 0 to 400mV level in one of the LMX. 

    --

    Regards,

    Kiran

  • 0 in reply to Kiran Kumar R
    TI__Guru** 107260 points

    Hi Kiran,

    The loop filter on LMX2820 is fine.

     Except for the loop filter, could you point out to me exactly what were modified? I don't see much difference between the schematics.

  • 0 in reply to Noel Fung
    Intellectual 265 points

    Hi Noel, 

    Other than loop filters, the 120MHz VCXO for LMK04832 is changed to 100MHz VCXO. 

  • 0 in reply to Kiran Kumar R
    Intellectual 265 points

    Hi Noel,

    The issue got resolved. We are running an application to program the LMK and LMX devices. There was a small bug in the application. We were giving the Hex register values exported from the Ticspro tool as an input to our application. It was skipping the last register programming (last line in the code, say if the code has n lines it was programming the n-1 lines skipping the last line of the hex file). The last register programing was a VCO calibration which was getting skipped while programming. 
    Even this register was not getting programmed for our initial designed frequency, but still the LMX2820 PLL was locking. Is this because our initial frequency for LMX was in VCO7 band (our new design frequency is in VCO6 band) which may not affect the PLL locking even without programming the register?. In both cases the last register programmed was R0 with data 6670H.
    --
    regards,
    Kiran