Hi,
I'm having an issue where I have a two board setup and am probing the same outputs of two LMK04828Bs that are programmed the same way and I'm trying to get these two outputs to have a deterministic phase.
Some notes:
- same 10MHz reference to each CLK0
- each LMK04828B has a 160MHz VCXO (separate ICs on each board, but same model producing the 160MHz)
- each getting 1.8V SYNC pulse on the SYNC input
- output clocks are:
- 192 MHz
- 2 MHz SYSREF
- nested 0-delay mode with SYSREF as feedback clock
The 192 MHz is key for what we are trying to do, and right now we need to get this to work with a 10MHz reference. The SYSREF frequency is less important. It was just chosen to be in integer submultiple of the 192MHz.
What I do is program the LMKs with the registers from the HexRegisterValues.txt file, and then the two chips expectedly come up with the 192MHz clocks at a fixed phase (typically out of phase, sometimes a full 180deg, but it's possible they're in phase). If I reprogram the chips with the full HexRegisterValues.txt file then the LMKs likely come up with outputs with different phases than prior, but as expected these phases are non-deterministic.
When I do a procedure to apply the SYNC pulse (includes SYSREF_CLR=1, SYNC_DIS*=0, DDLY_PDs=0, normal sync mode, SYNC_1SHOT_EN=0, SYNC_POL=0), what I see on an oscilloscope on the SYNC pulse falling edge is that the 192MHz clocks are in phase right after the sync pulse. However, if I retrigger/recollect on the oscilloscope later, the clocks are again out of phase (and seemingly at the phases prior to the SYNC). We've seemed to narrow this happening to after a few milliseconds.
To confirm this, we've been doing the initial config with HexRegisterValues.txt to get the phases to be near 180deg out of phase, then doing the SYNC pulse (where we trigger and verify they become in phase after SYNC) then capture data later or view it in realtime and see that they've appear to drift to the ~180deg phase difference again
Any idea what could be going on here? Thanks!
