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Hi,
I'm having an issue where I have a two board setup and am probing the same outputs of two LMK04828Bs that are programmed the same way and I'm trying to get these two outputs to have a deterministic phase.
Some notes:
The 192 MHz is key for what we are trying to do, and right now we need to get this to work with a 10MHz reference. The SYSREF frequency is less important. It was just chosen to be in integer submultiple of the 192MHz.
What I do is program the LMKs with the registers from the HexRegisterValues.txt file, and then the two chips expectedly come up with the 192MHz clocks at a fixed phase (typically out of phase, sometimes a full 180deg, but it's possible they're in phase). If I reprogram the chips with the full HexRegisterValues.txt file then the LMKs likely come up with outputs with different phases than prior, but as expected these phases are non-deterministic.
When I do a procedure to apply the SYNC pulse (includes SYSREF_CLR=1, SYNC_DIS*=0, DDLY_PDs=0, normal sync mode, SYNC_1SHOT_EN=0, SYNC_POL=0), what I see on an oscilloscope on the SYNC pulse falling edge is that the 192MHz clocks are in phase right after the sync pulse. However, if I retrigger/recollect on the oscilloscope later, the clocks are again out of phase (and seemingly at the phases prior to the SYNC). We've seemed to narrow this happening to after a few milliseconds.
To confirm this, we've been doing the initial config with HexRegisterValues.txt to get the phases to be near 180deg out of phase, then doing the SYNC pulse (where we trigger and verify they become in phase after SYNC) then capture data later or view it in realtime and see that they've appear to drift to the ~180deg phase difference again
Any idea what could be going on here? Thanks!
Hi,
I would be suggesting to go over the multi-clock sync app note to know more about conditions for 0-delay mode and multi-clock sync approach.
Here, I can observe the devices are not configuring in fully 0-delay mode and see the non-deterministic phase.
You can try with the 0-delay mode along with divider reset approach, where set the internal SYNC with SYNC_PLL1_DLD --> 1 (which will generate the SYNC once PLL1 will lock) and keep the sync enable to required channels in reset mode (SYNC_DISx --> 0) to resetting the dividers.
Thanks!
Regards,
Ajeet Pal
Thank you for responding. I had read this app note prior to posting. I believe the only thing I had not done prior was set SYNC_PLL1_DLD (and I also tried setting SYNC_PLL2_DLD), and even after trying this I am still getting the same results.
Attached is my HexRegisterValues.txt file.
R0 (INIT) 0x000090 R0 0x000010 R2 0x000200 R3 0x000306 R4 0x0004D0 R5 0x00055B R6 0x000600 R12 0x000C51 R13 0x000D04 R256 0x010070 R257 0x010155 R258 0x010255 R259 0x010301 R260 0x010422 R261 0x010500 R262 0x010673 R263 0x010703 R264 0x010870 R265 0x010955 R266 0x010A55 R267 0x010B01 R268 0x010C22 R269 0x010D00 R270 0x010E70 R271 0x010F30 R272 0x011070 R273 0x011155 R274 0x011255 R275 0x011301 R276 0x011422 R277 0x011500 R278 0x011673 R279 0x011703 R280 0x011870 R281 0x011955 R282 0x011A55 R283 0x011B01 R284 0x011C22 R285 0x011D00 R286 0x011E7A R287 0x011F03 R288 0x012070 R289 0x012155 R290 0x012255 R291 0x012301 R292 0x012422 R293 0x012500 R294 0x012670 R295 0x012733 R296 0x012870 R297 0x012955 R298 0x012A55 R299 0x012B01 R300 0x012C02 R301 0x012D00 R302 0x012E70 R303 0x012F30 R304 0x013070 R305 0x013155 R306 0x013255 R307 0x013301 R308 0x013422 R309 0x013500 R310 0x01367B R311 0x013703 R312 0x013820 R313 0x013903 R314 0x013A06 R315 0x013B00 R316 0x013C00 R317 0x013D01 R318 0x013E03 R319 0x013F0D R320 0x014001 R321 0x014100 R322 0x014200 R323 0x01431D R324 0x0144FF R325 0x01457F R326 0x014618 R327 0x01470A R328 0x014806 R329 0x014946 R330 0x014A06 R331 0x014B06 R332 0x014C00 R333 0x014D00 R334 0x014EC0 R335 0x014F7F R336 0x015013 R337 0x015102 R338 0x015200 R339 0x015300 R340 0x015405 R341 0x015500 R342 0x015605 R343 0x015700 R344 0x015805 R345 0x015900 R346 0x015A01 R347 0x015BDA R348 0x015C20 R349 0x015D00 R350 0x015E00 R351 0x015F3E R352 0x016000 R353 0x016114 R354 0x016244 R355 0x016300 R356 0x016400 R357 0x0165A0 R369 0x0171AA R370 0x017202 R380 0x017C15 R381 0x017D33 R358 0x016600 R359 0x016700 R360 0x0168C0 R361 0x016959 R362 0x016A20 R363 0x016B00 R364 0x016C00 R365 0x016D00 R366 0x016E1B R371 0x017300 R386 0x018200 R387 0x018300 R388 0x018400 R389 0x018500 R392 0x018800 R393 0x018900 R394 0x018A00 R395 0x018B00 R8189 0x1FFD00 R8190 0x1FFE00 R8191 0x1FFF53
Below is a Python snippet for applying a sync:
# set to Normal SYNC spi_dev.write_val(0x139, 0) # set to re-clocked SYNC # spi_dev.write_val(0x139, 1) # set SYSREF_CLR (reg 0x143, bit 7) spi_dev.write_val(0x143, 0x95) # turn off SYNC disable bits spi_dev.write_val(0x144, 0) print("about to sync...") time.sleep(1) gpio_lmk_sync.set_value(1) time.sleep(0.1) gpio_lmk_sync.set_value(0) print("sync performed") time.sleep(0.1) # turn on SYNC disable bits spi_dev.write_val(0x144, 0xFF) # clear SYSREF_CLR (reg 0x143, bit 7) spi_dev.write_val(0x143, 0x15) # set back to SYSREF continuous spi_dev.write_val(0x139, 3)
Hi,
The hex register config file looks good, except can further increase the PLL2_PFD frequency to 32MHz (to improve the phase noise performance), also need to run the test with below sequence:
1. Initially, load the config file (LMK04828_e2e_updated.tcs), with program SYNC_PLL1_DLD=1, and SYNC_DIS0, SYNC_DIS2, ..., SYNC_DIS12=0 to enable reset. The SYSREF divider does not need to be reset and SYNC_DISSYSREF will not have an effect, because the SYSREF output is used as the zero-delay feedback which can only have one phase (determined by reference input).
2. Wait for PLL1 to lock
3. When PLL1 locks, the output dividers will be released from synchronization simultaneously, ensuring every LMK device sees the reference clock at the same phase.
4. After PLL1 locks, program SYNC_DIS0, SYNC_DIS2, ..., SYNC_DIS12=1 to prevent SYSREF edges from triggering divider reset again.
5. Set SYSREF_MUX to continuous.
Please go over the above sequence and let me know, if you still see the issue.
Thanks!
Regards,
Ajeet Pal
Thank you! I think it was having SYNC_DISSYSREF enabled that was preventing the SYNC from occurring.
Prior to your post I had just got it seemingly working in Dual Loop non-ZMD mode, but with your help it's working in ZMD mode.
To add some clarification to this, I'm now noticing that the SYSREF are never synced and out of phase between the two boards. I could get around this by doing two syncs (one first in Dual Loop where SYNC_DISSYSREF=0, then one in Dual Loop ZMD with SYNC_DISSYSREF=1), but if there's another way I'm all ears.
Hi,
May be I am not able to get your point here.
Are you able to get the synced output or not? can you please elaborate more?
Thanks!
Regards,
Ajeet Pal