• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 22 subscribers
  • Views 559 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMK04610: Single shot Sysref

LMK04610: sysref generation requirements

Daniel Sternesky
Prodigy 40 points
Part Number: LMK04610

I am trying to use the LMK04610 to generate a SYSREF pulse on one of the output clock pins. I am currently using the part in bypass mode (no PLLs activated, just outputs a copy of the input clock). From what I understand, in order to generate a series of SYSREF pulses on the output:

1. The SYNC pin needs to be configured as an input and enabled

2. SYNC_PIN_FUNC needs to be 01 for SYSREF generation

3. The pulse count needs to be set to some number between 1 and 32

4. The SYSREF_EN_CHx needs to be asserted for the desired channel

I have double checked that all of these registers read as they should. What am I doing wrong?

Thanks,

Daniel

  • 0
    TI__Mastermind 20900 points

    Hello Daniel,

    Please note that it is not possible to trigger a SYSREF pulse in distribution mode unless a clock is present on the output of the PLL2 prescaler, implying a need to enable PLL2 (regardless of whether PLL2 is used).

    regards,

    Julian

  • 0 in reply to Julian Hagedorn
    Prodigy 40 points

    Julian,

    I suspected this might be the problem, so thank you for verifying. I am now trying to use PLL2 only, without using the VCXO of PLL1. However, when I program the chip, I see output clocks that are not at all what I programmed it to be. I don't think PLL2 is operating properly, and as far as I can tell it is not locking. Can you tell me if there is something wrong with the way I am setting up PLL2? Here is my register file. /cfs-file/__key/communityserver-discussions-components-files/48/PLL2_5F00_en_5F00_78_5F00_125_5F00_MHz.txt

  • 0 in reply to Daniel Sternesky
    TI__Genius 12560 points

    Hi Daniel,

    It seems the above configuration file doesn't set PLL2_NDIV properly and not able to lock the PLL.

    Here, I am attaching the latest config file for the CLKin1 input frequency 78MHz and should able to lock the PLL2.

    Let's try this and see the performance.

    LMK04610_PLL2.tcs

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 40 points

    Ajeet,

    We are getting closer. This does output the desired frequencies on the desired channels. However, when I configure SYNC pin function as "Sysref request" and set one of the output channels to SYSREF functionality, and then toggle the SYNC pin, I do not get the expected behavior of a few SYSREF pulses on the output according to the number of pulses I have assigned in the outputs tab. I am seeing the PLL2_LCK_DET is now checked, so PLL2 is definitely locking. Also, I am testing all of this on the evaluation board.

    I have two questions:

    1. I have been following the datasheet recommended programming sequence, but it seems that in the working example that you gave me, registers 0x85 and 0x86 are reading 0x01, and register 0xF6 reads 0x00. Why is this different?

    2. Is there something else I need to select in order to enable SYSREF pulse generation besides what I mentioned (change SYNC pin function and enable SYSREF at output and select number of output pulses)?

  • 0 in reply to Daniel Sternesky
    Prodigy 40 points

    Ajeet,

    I figured out what the problem was, it was a problem with my test setup. The SYSREF functionality seems to be working now. I am still curious about question 1 I posed above. Let me know if you have information on that for me, and then I will mark this resolved.

    Thanks,

    Daniel

  • +1 in reply to Daniel Sternesky
    TI__Genius 12560 points

    Hi Daniel,

    Thanks for the pointing out the registers settings deviation.

    These registers were auto updated and differ the required values. You can change these register values based on programming sequence and it should work fine.

    Register 0x85 = 0x00

    Register 0x86 = 0x00

    Register 0xF6 = 0x02

    Can you let me know, what is the setup issue you observed for the SYSREF pulsar generation?

    Regards,
    Ajeet Pal 

  • 0 in reply to Ajeet Pal
    Prodigy 40 points

    Ajeet,

    Thank you for the information. I just had the trigger on my oscilloscope set too low, so it was not showing the SYSREF pulses. I looked through the registers between the setup I was using and the one you gave me, and I believe the key was register 0x6D bit 2, which makes PLL2 lock detect not affected by LOS. As I understand, LOS is related to the external VCXO and PLL1, which we were not using in this case. Thank you for the help.

    Regards,

    Daniel