Other Parts Discussed in Thread: LMK5B33216, LMK05318
Hi,
For a project where several integrated devices need to be synchronized with the same clock, we are looking for a low-jitter clock generator.
The IC should be able to generate up to 8 identical LVDS clocks from a 1 to 6 MHz FPGA clock with a x16 multiplication factor (e.g., get 48 MHz output clocks from a 3 MHz reference input clock). Plus, we want the output clocks to be edge aligned with the input reference clock, so the IC should also integrate a zero-delay mode (ZDM).
We have identified the LMK05318B that seems to meet our requirements but the datasheet is confusing about ZDM. For example, is section 5:
“The DPLL can phaselock to a 1-PPS (pulse-per-second) reference input and support optional zero-delay mode on one output to achieve deterministic input-to-output phase alignment with programmable offset.”
First question: is this mode also compatible with conventional reference input clock other than a 1-PPS reference?
Second question: as far as we understand the datasheet, the ZDM feature seems to be only available on OUT7 channel. Is that correct? Or could we expect to get ZDM on all channels since they can all share the same input clock from APLL1 for example?
Thank you
Maxime
