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LMK04610: zero delay mode settings

Part Number: LMK04610

Hello,

I am having trouble getting the zero delay mode to work on the design I am trying to generate. In feedback mode (setting on PLL2 tab of TICS pro software) the PLL2 locks, and the output clocks are what I expect them to be. However if I switch it to OUTPUT5 or OUTPUT6 for zero delay mode, the output frequencies jump up ~4MHz and the PLL is no longer locked. I notice when I change this setting that the frequency in the PFD + LD box changes. Do I need to make the output of channel 5 or channel 6 match the output of the prescaler? What else do I need to consider for zero delay mode to operate?

Thanks,

Daniel

  • Hi Daniel,

    To change from feedback path to zero delay loop back mode (OUTCH5 / OUTCH6), you need to ensure the OUTCH5_DIV / OUTCH6_DIV values to be "1", if you are not changing the PLL2_NDIV settings. Otherwise the total feedback divider values should be multiple of PLL2_NDIV and OUTCH5_DIV to lock the PLL2.

    Would be great, if you can share the used TICS Pro config file to look on the settings.

    Thanks!

    Regards,
    Ajeet Pal

  • Ajeet,

    This was indeed the issue. I am wondering, since we need to use zero delay mode in this application, and we need either clock5 or 6 to be at ~2GHz (the divide by 3 output of the prescaler), we will not be using this clock for anything else. Do we need to take some special care about what we do with the ouptut? I am assuming we can just terminate it to ground at 50 ohms. Is this the case?