LMK04821: PLL1 occasionally loses lock

Hello Amy,

After looking at your TICS Pro file, I believe the problem may be that your SYSREF is not set up correctly. If you go to the SYNC/SYSREF tab, and then look to the right of the window, your SYSREF_CLR is enabled, and it should not be if you want to have a SYSREF output (notice the message that says that in red). Make sure to uncheck that box. What is going on internally is that register ensures no unwanted pulses occur (more information about this on page 41 of the data sheet), which may be the reason your PLL1 is coming from unlocked to locked state.

If this is not the case, I believe this lock state changes could be coming from how the external loop filter was designed. So with your reply, please make sure to include that information (resistor and capacitor values, topology used, loop bandwidth desired, and external VCO gain or data sheet) to best support you. You can also you TI's PLLatinum Sim tool to design your loop filter based on your loop bandwidth and external VCO gain (can download it here).

Good Luck,

Andrea

Hello Guo,

After looking over your TICS Pro, the data sheet, and running my own loop filter design simulations, there seems to be three problems:

1) Even though I know TICS Pro says otherwise and doesn't show an error, the N-Divider does not accept N = 1 values. This can lead PLL1 to unlock. This information can be found in the data sheet on p. 85 and on my screenshot below. Therefore, I have also included my TICS Pro file, to give a suggestion to your own file  LMK04821_PLL1Lock_LoopFilter.tcs..

2) When I inputted your loop filter into PLLatinum Sim with Fpd, CLKin1 frequencies, and charge pump current as shown in your TICS Pro file, I got a very low phase margin, making your design unstable and causing your PLL1 to unlock. If all that is correct and you are aiming to obtain a loop bandwidth of 0.166 kHz, then I would recommend you use C1539 = 3.9 nF, C1538 = 180 nF, and R138 = 18 kΩ if you decide to keep Fpd = 5MHz (as I demonstrated in my attached TICS Pro file). If you would like further help on this design, please let me know what loop bandwidth you are aiming to achieve.

3) Regarding the slew rate consideration you mentioned, from my calculations, you are not hitting the minimum requirements for slew rate on the data sheet, which is expected when using sine waves. This could also be a reason your PLL is not locking.

Good Luck,

Andrea

Hello Xiaoyang,

You are correct, PLLatinum Sim can only do one PLL simulation at a time, and it cannot be configured in SYSREF and Dual-PLL mode. However, for the loop filter, only the Fpd, charge pump current and VCO gain matter, so the values of the dividers are not important. However, you do want to keep in mind that if you change the output frequency, you also have to change the VCO gain (i.e if your VCO frequency is 100 MHz and you VCO gain is 0.0025 MHz/V and you change to 10 MHZ VCO frequency, then you have to change your VCO gain to 0.00025 MHz/V).

I have a few other ideas as to why your PLL1 is still not locking:

1) Based on your input waveform, your slew rate seems to be lower than the minimum recommended spec (I'm calculating 0.0765 V/ns and the minimum is 0.15 V/ns). This can cause you PLL to unlock. I would suggest you change your signal to a square wave.

2) If your input is spurious, I would suggest you increase your N and R dividers to divide down that unwarted signal. For instance you can make Fpd = 1 MHz, and your dividers to R = N =1. You would also have to change your loop filter to C1539 = 2.2 nF, C1538 = 100 nF, and R138 = 56 kΩ.

3) If you changed the PLL1 window size to lower than 43 ns, I would suggest you raise it again and make it as big as possible (43 ns is the max). This can lead to longer range of locking, which could solve your problem. 

If none of that works, I would suggest to physically check with a voltmeter your VCO voltage and see if its Vcc/2. If so, your PLLs are locking and its just a problem with the hardware. If that checks out, then I would suggest to change your "Other" settings under "I/Os." The PLL1 LD and PLL2 LD can be set to output the PLL1_N and PLL1_R (as shown in the picture below) and that would route those signals coming out of those nodes to a scope.

I would also suggest going through this link that goes over general ideas of what to do if your PLLs are out of phase.

Hello Xiaoyang,

I am glad those recommendations worked. PLL1 LD and PLL2 LD, by default, refer to the two LED lights telling you if PLL1 and PLL2 are locked. That drop down menu allows you to change the default and have other values/states/signals be routed through those pins. If you set PLL1 LD to PLL1 N, the signal coming out of PLL1's N divider will be routed through that pin, Therefore, you can connect those pins to an oscilloscope and see the signal at that node. I believe the EVM even has test points for those nodes so you don't have to solder the board. Hope this helps!

Best,

Andrea