Other Parts Discussed in Thread: ADC12DJ3200
Question,
If trace lengths are matched, what are the correct delays for two pairs of DEVICE and SYSREF clocks going to an FPGA JESD block and the ADC12DJ3200?
The ADC dev clock is running at 3 GHz, the FPGA dev clock 300 MHz, and the SYSREF clock at 18.75 MHz.
