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Original question:

LMK04826: Multi LMK Synchronization -- Using LMK Sync Pin

LMK04826: LMK DCLK and SDCLK Delays

Nicholas Strong
Prodigy 90 points
Part Number: LMK04826
Other Parts Discussed in Thread: ADC12DJ3200, LMK04828, LMK04832, LMK04808

Question,

If trace lengths are matched, what are the correct delays for two pairs of DEVICE and SYSREF clocks going to an FPGA JESD block and the ADC12DJ3200?

The ADC dev clock is running at 3 GHz, the FPGA dev clock 300 MHz, and the SYSREF clock at 18.75 MHz.

Edit:

Sorry this is for the LMK04828

I reposted here: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1165773/lmk04828-devclk-and-sysref-delays

  • 0
    TI__Genius 12560 points

    Hi,

    If your system has only 1 ADC12DJ3200 and 1 FPGA, the 2 pairs of JESD204B clocks (DEV CLK and SYSREF) doesn't necessary to have length match but DEV CLK and SYSREF to each device should be length matched.

    Whereas, if you have multi device sync (multiple ADCs) scenario, the JESD204B clocks pairs should be synced through SYNC feature and should have length matched traces to ADCs.

    Regarding the ADC clock frequency 3GHz, LMK04828 supports LVDS/HSDS/LVPECL/LCPECL outputs, which has lower amplitude at higher frequencies. Below is the LVPECL/LCPECL output plot over the frequency FYR. Do the analysis for the required clock amplitude for the ADC and choose the output format. 

    However there is an LMK04832 (pin compatible to LMK04828), which support CML output and have higher amplitude at higher frequencies.

    Thanks!

    Regards,
    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 90 points

    Hi Ajeet,

    This still doesn't speak on delays. Should all the delays be 0 for the dev and sysref clocks?

  • 0 in reply to Nicholas Strong
    Prodigy 90 points

    Also, does the LMK output LVDS at the correct voltage levels at 3 GHz?

  • 0 in reply to Nicholas Strong
    TI__Genius 12560 points

    Hi,

    Regarding the actual delay settings for the DCLK and SYSREF clocks depends on the division values and the required setup and hold timing at the receiver end. There is an DCLK to SDCLK skew in the range of |50ps| and based on setup and hold timing requirement at ADC, the delay need to be optimized.

    Hence, in the beginning you can keep the same delay values for both and if needed you can may need to adjust the value for DCLK or SDCLK. You can follow the section 9.3.4 in the LMK04828 datasheet for SYSREF to Device clock alignment exercise.

    The differential amplitude for the LVDS format reduces drastically at higher frequency than LVPECL/LCPECL.

    LMK04808 has the similar output buffer as LMK04828.

    Thanks!

    Regards,
    Ajeet Pal