Other Parts Discussed in Thread: DAC38J84, , LMK04828
We are using three LMK04826B on our custom board. We are giving input of fixed 100 MHz to OSCin to three LMK's.
The following clocking scheme is implemented.
We are using VCO of 1900MHz and generate required clock for both FPGA and Dac38j84.
Dac clock - 1900 MHz
Sysref - 3.7109375 MHz
FPGA clock - 118.75MHz
In order to get clock and sysref aligned between multiple LMKs. We are generating a single pulse from FPGA and passing over sync pin of all the LMK's
1. Trace Lengths between FPGA -- LMK 1, FPGA -- LMK 2, FPGA -- LMK 3 are not same.
By monitoring the SYNC pin of LMK 1 and LMK 2, the delay between the pulses is 120 ps. We are using SYNC_1_shot_EN.
When we are monitoring the LMK 1 and LMK 2 Sysref outputs, they are alligned with zero delay.
It is difficult to monitor 1900 MHz clock between LMK 1 and LMK 2, So we went for device clock of 475 MHz. At 475 MHz, Delay between LMK 1 and LMK 2 is 320 ps. It is same across multiple power cycles.
If Sysref are aligned perfectly, why there is delay at Device clocks ??
Is it required to maintain same Trace lengths between (SYNC pins -- FPGA ) for all LMK's ??
2. If they are not length matched, What is the minimum skew that LMKs can adjust to synchronize the outputs of different LMK's.
3. Is it required to give SYNC Synchronous to the LMK Input Clock ??
4. Same SYNC is used for all LMKS. If we toggle SYNC pin of LMK 1, at that point, LMK 1 Clock dividers will reset and clock will align with respect to rising edge of SYNC.
Now there is some Discontinuity in the OSCin Clock of LMK 3. So at the Same SYNC event, how clock outputs of LMK 3 will be aligned, since input to LMK 3 is not proper at SYNC event.
5. What happens if input to LMK is switched of for some short Duration. PLL comes out of lock. We will get output clocks with Jitter . What happens if we switch on Input again.
6. What are the alternates way to acheive Multi LMK synchronization for the given clocking scheme. (Any Solution with Zero Delay Mode ??)
7.We need alignment of DAC NCO.To do this we are doing NCO reset on Sysref. But we are unable to achieve it at 600 MHz NCO Frequency.
We are giving reset pulse to SYNC pin of LMK. From LMK we are routing this reset signal on to LMK Sysref Path. From this Path we are using this pulse to reset NCO.
Will there be any delay between the Sysref paths of two LMKs ??
Please check the NCO configurations attached for 600 MHz Output.
dac_write 0x2f 0x0001 dac_write 0x30 0x7fff dac_write 0x0D 0x0400 dac_write 0x02 0x20C2 dac_write 0x02 0x20D2 dac_write 0x12 0x0000 dac_write 0x13 0x0000 dac_write 0x14 0xE50D dac_write 0x15 0x9435 dac_write 0x16 0x50D7 dac_write 0x17 0xE50D dac_write 0x18 0x9435 dac_write 0x19 0x50D7 dac_write 0x1F 0x2220
