I use the LMK01801 in several designs with Pin Control mode configured.
In one of the designs, I used the LMK01801 with a 1GHz clock at CLKin0 input and set the CLKout0-7 to LVDS clocks div by 1 (CLKoutTYPE_0 and CLKoutDIV_0 and are set to LOW ).
I set both CLKoutTYPE_1 and CLKoutTYPE_2 to LOW so all clks outputs are set to LVDS.
I use the CLKout7 LVDS (1GHz ) output to feed back the CLKin1.
When I set the EN_PIN_CTRL to LOW and CLKoutDIV_2 to LOW (div by 8 as shown in Table 5-2) I get an output clock at CLKout12-13 of 125MHz (= 1GHz/8) as expected.
But when I set the EN_PIN_CTRL to HIGH and CLKoutDIV_2 to LOW (div by 4 as shown in Table 5-3 ) I get an output clock at CLKout12-13 of 500MHz which matches div by 2 and not a clock of 250 MHz (= 1GHz/4) as expected.
I tried to implement the same setup (with different clocks 600MHz ) on other designs that also use the LMK01801 and once again get an output at CLKout12-13 divided by 2 (300MHz) instead of by 4 (150Mhz) as expected.
From the correspondence above it seems that this is a familiar issue.
Is there any solution ????
