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CDCI6214: About Congiguration and Initialization

Haitong Xu
Prodigy 20 points

Part Number: CDCI6214

Now we have the following problems. I hope someone can put forward suggestions

1. Our refsel and eepromsel are connected to the ground, so 1110110 is selected for SLAVE ADRRES. After power on, the device will be reset for 500ms through reset pin. Then configure from the 0x3F register to the 0x00 register according to the protocol shown in figure 27. Then write a 1 to recal, select the EEPROM page，unlock the eeprom , start the commit operation, force a crc update,read back crc value and store it in the eeprom.This procedure is according to page 29 of datasheet. However, the output frequency is always 94MHz, which will not change for our configuration changes. Then we try to write the register(like CH2_CTRL3)and read it back, and the results are all 0000,which is just like I never write it in successfully.

2. If we remove the resistance of eepromsel, that is, let eepromsel pin high Z, and change SLAVE ADRRES to 1110100, there will be no output signal

  • +1
    TI__Mastermind 20900 points

    Hello,

    It looks that the PLL is unlocked. Please confirm if a reference clock is enabled.

    also note the power up sequence described in the datasheet:

    If EEPROMSEL is tristated, REFSEL should be tristated too. That ensures you enter fallback mode.

    regards,

    Julian

  • 0 in reply to Julian Hagedorn
    Prodigy 20 points

    Thanks for reply. We haven't let it work well now. l have three questions now.

    Q1：About he working mode of CDCI6214, when EEPROMSEL and REFSEL are tristated,the chip is on the fall back mode .What lknow about it is that on this mode , we can program the chip by i2c. However,What l do not know is that, on this mode,can this chip work with the output signal which we want? To speak another way, is tis mode specially used just for programming by serial i2c interface? or it can be also used for normal operating conditions ? which means we can get the output signal with the frequency we want(P.S.:What l understand is that the chip has two conditions : programing condition and normal operating condithion mentioned above.)

    lf it can be also used for nomal operating conditons, then, on this mode, is eeprom used? And , on this mode,what is the ref input signal?  As l Know, REFSEL high and REFSEL low both indicate one kind of ref input signal.So, on this mode ,what about the ref input signal?

    Q2: Our initialization and configuration procedure is:

    (1): set REFSEL and EEPROMSEL MID(get rid of the pull down resistor) , power on , reset delay release.

    (2): program the register(not eeprom) from 0x44 to 0x00(ignore some registers,all bits of which are reserved)

    (3):accordng to the datasheet,we do the following point 2 to point 8(highlighted in the following picture)

    (4) power dowm , set RESEL and EPROMSEL low(use the pul down resistor), power on , we think it should work on the normal operating condition.

    l want to ask : is our procedure correct?

    Q3:When it is on the fall back mode, we pocgram all the registers we need to conigure(I can successfully readback the value l have written into the register), and unok the eeprom and start the commit operation according to the point 4 and point 5, after doing this, we force a crc update, and then readback crc, but by internal ila of FPGA,l see the read back crc value contains 0x0000 all the time, what is the problem?

  • 0 in reply to Haitong Xu
    TI__Mastermind 23280 points

    Haitong,

    I believe that Jennifer is working with you on this in a separate thread. I will mark this one as closed.

    Thanks,

    Kadeem