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Original question:

LMK05318B: Using the LMK5318B part and having problems getting the DLL to lock

LMK05318B: Facing DPLL Phase and Frequency loss of lock for 250MHz differential input clock

MURALI PT
Prodigy 70 points
Part Number: LMK05318B
Other Parts Discussed in Thread: LMK05318

We are using LMK05318B device and feeding 250MHz differential clock to this device and we have enabled the internal 100 ohm termination in the configuration and there is Series AC capacitor 0.1uF present on this path.

We are observing LOPL_DPLL & LOFL_DPLL interrupt during operation. Please let us know how we can solve this problem? I am attaching Gamora_PFE_LMK05318B_GEN2_PTP_rev4.tcs tcs file in this ticket.

  • 0
    TI__Mastermind 28590 points

    Hi Murali,

    We'll review the configuration and update you.

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 70 points

    Issue resolved if we change the clock frequency to 156.25MHz instead of 250MHz.

  • 0 in reply to MURALI PT
    TI__Genius 10995 points

    Hello Murali,

    Do you need further assistance from us?

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    Prodigy 70 points

    For our design this solution looks Good. From device capability point of view, I would like to understand whether LMK clock generator is capable to clean the clock if the input clock frequency is 250MHz? How much should be the clock jitter on which this device will work effectively?

  • 0 in reply to MURALI PT
    TI__Mastermind 28590 points

    Hi Murali,

    I can't say I've ever had a problem with too much jitter.  Note that LMK05318B passes the the G.8262 Jitter Tolerance test.

    Because there are an infinite number of phase noise profiles which can result in the same amount of jitter, not to mention different jitter integration ranges.  As far as trying to break the part with too much jitter, I think it would depend on the actual location of the noise.  As jitter is the integration of phase noise, therefore I expect it could pass and fail for the same "jitter" value depending on where the noise is and what you choose your integration bandwidth to be.

    Then the other point is is what is the definition of breaking.  For example I could imagine a case where the DPLL LOPL becomes unasserted, but it is still effectively "frequency locked" -- and you could probably relax the phase lock thresholds to keep it from deasserting LOPL.

    As far as jitter cleaning effectiveness...

    • when using the LMK05318 as a DPLL, your jitter cleaning is going to occur above the DPLL LBW and clean to the quality of the XO/TCXO/OCXO used as XO input.
    • If using LMK05318 for clock generator, (or jitter cleaning using only the BAW) then, the jitter cleaning will occur above the APLL1 LBW.  Typically for the PLL1 (the APLL with VCBO) this is around 10 kHz but can be narrowed with lower charge pump current.

    Hope this helps.

    73,
    Timothy