• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 22 subscribers
  • Views 409 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2595EVM: Phase noise is different from the simulation PLLatinum Sim

Mark
Prodigy 57 points
Part Number: LMX2595EVM
Other Parts Discussed in Thread: LMX2595

Hello. We are testing the LMX2595EVM with SMA100B.  The frequency of reference clock from SMA100b is 100 MHz and Osc_doubler of LMX2595EVM is enabled. We find that at several frequencies, the measured phase noise at 1kHz and 10kHz offset do match what the data sheet specifices，but don‘t match the simulation results calculated by PLLatinum Sim. The comparison between measured results and simulation results are as follows.

It can be seen that at frequencies above, simulated results at 1kHz and 10kHz offset are much better than both measured results and specificed values of data sheet. Thus we think that the configuration we set in PLLatinum Sim might be unproper.

During operation of PLLatinum Sim, OSC noise is "data loaded" and the imported data is measured phase noise of 100 MHz reference clock from SMA100b. VCO noise and PLL noise are "Use Metrics", which are defult configuration. The loop filter is set according to the configuration in data sheet of LMX2595EVM.

Is there any possible reasons accounting for the mismatch between simulated results and measured results？

  • 0
    TI__Guru* 96830 points

    Hi Mark,

    What was the input clock power? Could you try 10dBm? If possible, use even higher output power with a limiter. 

    The goal is to increase the slew rate of the input clock, which has impact to the PLL phase noise.

  • 0 in reply to Noel Fung
    Prodigy 57 points

    Hello Neol,

    The output power of reference clock from SMA100b is 5dBm. We take you advice to set the power to 10dBm and the voltage on OSCinP port is about 200mV. The results are as follows. It turns out that measured results with 10 dBm input still cannot match the simulated reasults.

     

    We have also tried higher input power, like 15,20 and 25dBm. The voltage on OSCinP port remains nearly 200mV and the measured results are similar to the results measured with 5dBm input power, which are still quite different from the simulated results. We also found that with higher input reference power, like 20 and 25dBm, the phase noise at all frequency offsets would even degrade and increase by 1-2 dB. 

    Is there any other possible reasons for the mismatch between simulated results and measured results?

  • 0 in reply to Mark
    TI__Guru* 96830 points

    Hi Mark,

    it does not seem right, with 10dBm, you should measure 2Vpp sine wave signal. 200mVpp is equivalent to -10dBm. Could you verify the voltage swing you have measured?

  • 0 in reply to Noel Fung
    Prodigy 57 points

    You're right. There is something wrong with our measurement of voltage. We've reconfigured and verified the voltage again. It was 2 Vpp with 10 dBm. And we measured the phase noise again with 10 dBm reference. However, the conclusion seemed not to change. There was still mismatch between simulated results and measured results.

    Is there any other possible problemes?

  • 0 in reply to Noel Fung
    Prodigy 57 points

    Let's put the problem of input reference power aside. However, we are more curious about the reasons for the difference between simulation and values specified by data sheet. We'd like to know whether our simulation configuration is proper for lmx2595?

  • +1 in reply to Mark
    TI__Guru* 96830 points

    Hi Mark,

    The simulation is straight forward and your configuration is correct. The discrepancy could be due to the metric we put in the simulation tool is not an average value. Other reason could be the slew rate of the input clock is not optimized. You may also try using a 200MHz 10dBm clock, this would increase the slew rate a little bit. 

  • 0 in reply to Noel Fung
    Prodigy 57 points

    Hi Noel,

    Thanks a lot for your suggestions! We will try using clock with higher slew rate. And we wonder if it is convient to provide average value for VCO noise and PLL noise and the data can be loaded into the simulation.  

  • +1 in reply to Mark
    TI__Guru* 96830 points

    Hi Mark,

    I will talk to the developer of the simulation tool, if this is doable, we will implement it in next update.

    At the moment, please keep using the existing version, and add a couple of dB in-band.