LMH1983: Hsync pulse and consecutive cycle

Part Number: LMH1983

Hi team

Regarding to the following thread:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/767500/lmh1983-question-about-lockstepsize-and-loss-of-lock-threshold/2846224?tisearch=e2e-sitesearch&keymatch=LMH1983%2520lockstepsize#2846224

I see Alan mentioned that for 3 consecutive cycle with no lock the no lock status would assert, but then the datasheet says on the Loss of Lock Threshold register's description that during blanking there can have up to 5 missing Hsync pulses, and this value is usually set > 6.

My understanding is:

Hsync pulse: Reference XO edges

Consecutive cycle: PLL output cycle

Since the Loss of Lock Threshold register is set for the Hsync pulse, changing it does not directly affect this consecutive cycle, despite the detect window might be affected.

Could you confirm if my understanding on this is correct?

Regards