LMK05318: Frequence deviation tolerance for DPLL Primary and Secondary Ref clock Inputs.

Vaison Xia

Part Number: LMK05318
Other Parts Discussed in Thread: , USB2ANY

Hi, TI expert,

I am using LMK05318 on my board. I have 20ppm frequence deviation for DPLL Primary and Secondary Reference Clock Inputs (PRIREF_P PRIREF_N, SECREF_P SECREF_N).

For example, in my test:

80566140 Hz input via TICS Pro software makes LMK05318 DPLL lock.

80566406 Hz via TICS Pro software does NOT make LMK05318 DPLL lock(LOFL_DPLL=1), even other settings are the same.

80566140 Hz is from our real measurement on one board. 80566406 Hz is from our calculation.

What is the frequence deviation tolerance (? ppm) for DPLL Primary and Secondary Reference Clock Inputs? Thanks!

I cannot measure every board to determine the accurate frequence for DPLL Primary and Secondary Reference Clock Inputs.

Other condition in my test :

XO: 48MHz input with 25ppm. Use LMK05318 DPLL and APLL1, not use APLL2.

Thanks!

Vaison

over 1 year ago

0 Timothy T over 1 year ago

TI__Mastermind 28540 points

Hi Vaison,

Have you used the TICS Pro software to configure a profile for the LMK05318? (To confirm, you are using the LMK05318 or LMK05318B version?)

For the device to lock, it first needs to validate the reference, then it can lock to it. The Ref validation page under the LMK05381B wizard allows you to set an allowable values for the frequency detector so you may control the limits. When setting these limits the measurement is made against the XO, so worse case XO ppm error bust be considered vs. the worst case input ppm error.

- Once validated, the DPLL may then lock to the reference.

73,
Timothy

0 Vaison Xia over 1 year ago in reply to Timothy T

Prodigy 10 points

Hi, Timothy

Thanks for your reply! I am using LMK05318 (not LMK05318B) and I am using TICS Pro software to configure a profile for the LMK05318. In LMK05381 wizard, I saw "DPLL frequence lock detect", and by default , it is lock 1 ppm, unlock 10 ppm. Avg 2. Can I change to lock 10 ppm, unlock 20 ppm? My XO input is 48MHZ,25PPM.

After I changed those ppm values, I did not see any recalculation button for it. Should I just press "run script" button ?

I tried it with pressing "run script" button, the script ran and it was not able to lock with PRI_REF and SEC_PRIREF 80566406Hz input(the expected value from our Intel chip output).

With default DPLL frequence lock detect lock 1 ppm, unlock 10 ppm, if I input PRI_REF and SEC_PRIREF with 80566140Hz, the DPLL was able to lock.

Any idea? Thanks!

Vaison

0 Timothy T over 1 year ago in reply to Vaison Xia

TI__Mastermind 28540 points

Hi Vaison,

The DPLL frequency lock detect shouldn't be the issue. DPLL freq lock detect is comparing DPLL OUTPUT with REF INPUT. The DPLL will lock the OUTPUT to be 0 ppm to the INPUT.

- When you type a new number and press enter, the calculation is updated.

What I wanted to clarify is if the DPLL is even trying to lock. In the DPLL lock procedure.
1) Reference input must be validated.
2) Then the DPLL will start to lock.

Status page will show the situation.

On the Startpage, whatever detectors are enabled must pass for DPLL to select reference. Here, the input reference must be within 20 ppm of the XO. So if the XO is +/- 50 ppm. You may not even allow DPLL to lock to 0 ppm signal if XO = +50 ppm for instance.

Also, for confirming lock of APLL to XO, you may enable the BAW_LOCK detector... (on startpage)

Here on status page, after doing a readback...

1) XO should be valid, LOS_FDET_XO = 0.
2) LOL_PLL1 should be 0.
3) If BAW_LOCK is enabled, BAW_LOCK=1. Meaning APLL is locked to XO. (Note bad DPLL config can force APLL to rail and therefore BAW_LOCK could be 0 due to improper DPLL config -- remove/disable references/DPLL to debug this case)
4) The reference you want to lock to should be validated. This refers to the validations above all being met.
5) The DPLL will select a valid reference based on it's configuration options.
6) LOFL_DPLL = 0. Freq lock on DPLL. This typically happens pretty quick.
7) LOPL_DPLL = 0. Phase lock on DPLL goes low, depending on loop bandwidth this can take a while.

To better debug your problem, please go through the list of what's going on so we can identify where the problem is occurring. For instance, is it not locking because shifting the reference frequency is causing the reference to become invalidated and then the DPLL is no longer in lock.

Perhaps you could share the .tcs file you are using in your config?

73,
Timothy

0 Vaison Xia over 1 year ago in reply to Timothy T

Prodigy 10 points

Hi, Timothy

Thanks for your detailed information. I did further debug according to your suggestions.

BAW_LOCK was disable on my setting.

I changed frequence detect threshold PREREF to 20ppm (enable) or even 1ppm (enable), the result below is not changed.

80566140 Hz	Lock
80566240 Hz	Lock

80566406 HZ	Not lock

My target is to make 80566406 HZ to be locked in DPLL of LMK05318..

My XO 48MHz input to LMK05318: 48MHZ,25PPM.

Do you mean lmk5318 require 48MHZ+/-20PPM=960HZ for pri reference(PRIRFF) input range. From my result, it is not true.

Can you help? Thanks!

Vaison

0 Timothy T over 1 year ago in reply to Vaison Xia

TI__Mastermind 28540 points

Hi Vaison,

Please share your .TCS save file for your config.

73,
Timothy

0 Vaison Xia over 1 year ago in reply to Timothy T

Prodigy 10 points

Hi, Timothy,

I did not find the upload button to upload my file. I copied the content from "80566140Hz made DPLL lock.tcs" I used. That is working case with 80566140Hz PRIREF input. I will provide other non-working frequence case tcs file later this week (the board I debugged has other software running issue and I need to fix it this week this week ).

Thanks!

[SETUP]
ADDRESS=888
CLOCK=8
DATA=4
LE=2
PART=LMK05318
IFACE=I2C
ADDRESS_I2C=0x64
INTERFACE_SPEED=400

[PINS]
PINNAME00=REFSEL
LOCATION00=9
PINVALUE00=False
PINNAME01=HW_CTRL
LOCATION01=7
PINVALUE01=False
PINNAME02=PDN
LOCATION02=3
PINVALUE02=True
PINNAME03=GPIO0
LOCATION03=8
PINVALUE03=False
PINNAME04=GPIO1
LOCATION04=6
PINVALUE04=False
PINNAME05=GPIO2
LOCATION05=5
PINVALUE05=False
PINNAME06=Status0
LOCATION06=10
PINVALUE06=False
PINNAME07=Status1
LOCATION07=11
PINVALUE07=False

[MODES]
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[FLEX]
PLL1_BAW_CAPDAC=0
bFindAddressBtn=Find I2C Addr
i2cAddr=0
MATLAB_RUNTIME_DOWNLOAD_URL=www.mathworks.com/.../matlab-runtime.html
bGotoStartupPage=Goto Start Page
BAW_LOCK_PPM_THRESH=5
BAW_UNLK_PPM_THRESH=10
DCO_BUTTONS_GPIO_CTRL=1
DPLL_PL_LOCK_calc=311.72 ps
DPLL_PL_UNLK_calc=4.99 ns
OUT0_ACT_freq=156.25
OUT1_ACT_freq=156.25
OUT2_ACT_freq=156.25
OUT3_ACT_freq=156.25
OUT4_ACT_freq=156.25
OUT5_ACT_freq=156.25
OUT6_ACT_freq=100
OUT7_ACT_freq=100
VCO1_freq=2500.00000000001
VCO1_start_freq=2499875000
VCO1_stop_freq=2500125000
VCO2_freq=0
VCO2_start_freq=5500000000
VCO2_stop_freq=6000000000
bCALC_FREQPLAN=Calculate Frequency Plan
bCalcDPLL_PLD=Calculate
bDPLL_FDECR=Decrement
bDPLL_FINCR=Increment
bLoadCurrentVCOfreqRanges=Load current VCO freq ranges
bRUN_SCRIPT=Run Script
bTest=Test
hdr_act_freq=Actual Freq. (MHz)
sBAW_LOCK_ACCURACY_PPM=1
sBAW_LOCK_AVG=2
sBAW_TMEAS_LOCK_calc=19.20 ms
sBAW_TMEAS_UNLK_calc=3.84 ms
sBAW_UNLK_ACCURACY_PPM=5
sBAW_UNLK_AVG=2
sCH0_1_IN_freq=156.25e6
sCH0_1_MUX=1
sCH2_3_IN_freq=156.25e6
sCH2_3_MUX=1
sCH4_IN_freq=156.25e6
sCH4_MUX=1
sCH5_IN_freq=156.25e6
sCH5_MUX=1
sCH6_IN_freq=100e6
sCH6_MUX=1
sCH7_IN_freq=100e6
sCH7_MUX=1
sDPLL_DCO_STEP=0.01
sDPLL_DCO_STEP_ACT=0.00999958429379242
sDPLL_HISTCNT_calc=5.13 ms
sDPLL_HISTDLY_calc=2.57 ms
sDPLL_LBW=60
sDPLL_LBW_ACCURACY=5
sDPLL_LBW_ACT=60.29
sDPLL_LOCK_ACCURACY_PPM=1
sDPLL_LOCK_AVG=2
sDPLL_LOCK_PPM=1
sDPLL_PEAK=0.1
sDPLL_REF_COMMON_DIV=1000000000
sDPLL_TDC_freq=398.842277 kHz
sDPLL_TMEAS_LOCK_calc=19.20 ms
sDPLL_TMEAS_UNLK_calc=3.84 ms
sDPLL_UNLK_ACCURACY_PPM=5
sDPLL_UNLK_AVG=2
sDPLL_UNLK_PPM=10
sMAX_TDC_freq=400000
sMAX_TDC_simple=0
sMAX_XO_PPM=50
sPRIREF_ACCURACY_PPM=10
sPRIREF_AVG_COUNT=2
sPRIREF_EARLY_MARGIN=0
sPRIREF_EARLY_calc=6.40 ns
sPRIREF_LATE=0
sPRIREF_LATE_MARGIN=1
sPRIREF_LATE_calc=17.60 ns
sPRIREF_PH_VALID_calc=n/a; PRIREF > 2 kHz
sPRIREF_PPM_INVALID=26
sPRIREF_PPM_TIMER=4.17 ms
sPRIREF_PPM_VALID=20
sPRIREF_freq=80566140
sSECREF_ACCURACY_PPM=10
sSECREF_AVG_COUNT=2
sSECREF_EARLY_MARGIN=0
sSECREF_EARLY_calc=6.40 ns
sSECREF_LATE=0
sSECREF_LATE_MARGIN=1
sSECREF_LATE_calc=17.60 ns
sSECREF_PH_VALID_calc=n/a; SECREF > 2 kHz
sSECREF_PPM_INVALID=26
sSECREF_PPM_TIMER=4.17 ms
sSECREF_PPM_VALID=20
sSECREF_freq=80566140
sVCO1_freq=156.25e6*16*1
sVCO2_freq=0
sXO_freq=48.00e6
NVM_ERASE_PROG=0
REGCOMMIT_PG=0
bEXPORTEEPROMFILE=Export GUI Map --> EEPROM File
bIMPORTEEPROMFILE=(1b) Import EEPROM File --> GUI Map
bLoadDefaultEEPROMImageToGUIMap=(1c) Load Default EEPROM Image --> GUI Map
bLoadPage_from_GUIMap_to_GUI_Registers=Load GUI Map PAGE --> Register
bPROGRAMEEPROM=(3) Program EEPROM <-- SRAM
bREADBACKEEPROM=Read All EEPROM --> GUI Map
bREADBACKROM=Read All ROM --> GUI Map
bREADBACKSRAM=Read All SRAM --> GUI Map
bREG2EE=(1a) Commit Registers --> SRAM PAGE/GUI Map
cbEESLAVEADR=0
mtc_EEPROMdump=
mtc_USERNOTES=Enter User Notes
tc_DESIGNNAME=Enter Design Name
PLL1_DEN=1099511627776
PLL1_PFD_freq=24
VCO1_freq=2500
XO_freq=48
PLL2_DEN=16777216
PLL2_PFD_freq=138.888888888889
VCO1_freq=2500
VCO2_freq=5500
XO_freq=48
PRIREF_VALSTAT=1
SECREF_VALSTAT=1
bClearAllFlagStickyStatus=Clear All Flags
bReadStatus=Read Status
MUTE_DPLL_FRLOCK=0
OUT0_freq=156.25
OUT1_freq=156.25
OUT2_freq=156.25
OUT3_freq=156.25
OUT4_freq=156.25
OUT5_freq=156.25
OUT6_freq=100
OUT7_freq=100
PLL2PDIV1_freq=0
PLL2PDIV2_freq=0
VCO1_freq=2500
VCO2_freq=5500
sOUT7_DIV=25
PLL1_BAW_CAPDAC=0
bFindAddressBtn=Find I2C Addr
i2cAddr=0
OSCIN_DBLR_EN=0
OSCIN_RDIV=1
OSCIN_DBLR_EN=0
OSCIN_RDIV=1
OSCIN_DBLR_EN=0
OSCIN_RDIV=1
OSCIN_DBLR_EN=0
OSCIN_DBLR_EN=0
OSCIN_RDIV=1

0 Vaison Xia over 1 year ago in reply to Vaison Xia

Prodigy 10 points

Hi, Timothy,

Please ignore the tcs file "80566140Hz made DPLL lock.tcs" I posted yesterday. I copied from wrong place. Sorry for that.

Please use these two tcs files I copied now for your review. Thanks for your help!

The target is to make DPLL lock when using 80566406Hz PRIREF configuration input to USB2ANY. Can you help? Thanks!

80566140Hz made DPLL lock (cfg start page)02282023 V3.tcs
80566406Hz made DPLL not lock (cfg start page)02282023 V4.tcs

--------- 1. 80566140Hz made DPLL lock (cfg start page)02282023 V3.tcs --------------

[SETUP]
ADDRESS=888
CLOCK=8
DATA=4
LE=2
PART=LMK05318
IFACE=I2C
ADDRESS_I2C=0x64
INTERFACE_SPEED=400

--------2. 80566406Hz made DPLL not lock (cfg start page)02282023 V4.tcs-----------------------

[SETUP]
ADDRESS=888
CLOCK=8
DATA=4
LE=2
PART=LMK05318
IFACE=I2C
ADDRESS_I2C=0x64
INTERFACE_SPEED=400

[MODES]
NAME00=R0
VALUE00=16
NAME01=R1
VALUE01=267
NAME02=R2
VALUE02=565
NAME03=R3
VALUE03=785
NAME04=R4
VALUE04=1036
NAME05=R5
VALUE05=1300
NAME06=R6
VALUE06=1569
NAME07=R7
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VALUE08=2760
NAME09=R11
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NAME10=R12
VALUE10=3099
NAME11=R13
VALUE11=3336
NAME12=R14
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NAME13=R15
VALUE13=3840
NAME14=R16
VALUE14=4096
NAME15=R17
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VALUE16=4863
NAME17=R19
VALUE17=4864
NAME18=R20
VALUE18=5120
NAME19=R21
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NAME21=R23
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NAME22=R24
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VALUE35=10240
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[FLEX]
PLL1_BAW_CAPDAC=0
bFindAddressBtn=Find I2C Addr
i2cAddr=0
MATLAB_RUNTIME_DOWNLOAD_URL=www.mathworks.com/.../matlab-runtime.html
bGotoStartupPage=Goto Start Page
BAW_LOCK_PPM_THRESH=5
BAW_UNLK_PPM_THRESH=10
DCO_BUTTONS_GPIO_CTRL=1
DPLL_PL_LOCK_calc=311.72 ps
DPLL_PL_UNLK_calc=4.99 ns
OUT0_ACT_freq=156.25
OUT1_ACT_freq=156.25
OUT2_ACT_freq=156.25
OUT3_ACT_freq=156.25
OUT4_ACT_freq=156.25
OUT5_ACT_freq=156.25
OUT6_ACT_freq=100
OUT7_ACT_freq=100
VCO1_freq=2500.00000000001
VCO1_start_freq=2499875000
VCO1_stop_freq=2500125000
VCO2_freq=0
VCO2_start_freq=5500000000
VCO2_stop_freq=6000000000
bCALC_FREQPLAN=Calculate Frequency Plan
bCalcDPLL_PLD=Calculate
bDPLL_FDECR=Decrement
bDPLL_FINCR=Increment
bLoadCurrentVCOfreqRanges=Load current VCO freq ranges
bRUN_SCRIPT=Run Script
bTest=Test
hdr_act_freq=Actual Freq. (MHz)
sBAW_LOCK_ACCURACY_PPM=1
sBAW_LOCK_AVG=2
sBAW_TMEAS_LOCK_calc=19.20 ms
sBAW_TMEAS_UNLK_calc=3.84 ms
sBAW_UNLK_ACCURACY_PPM=5
sBAW_UNLK_AVG=2
sCH0_1_IN_freq=156.25e6
sCH0_1_MUX=1
sCH2_3_IN_freq=156.25e6
sCH2_3_MUX=1
sCH4_IN_freq=156.25e6
sCH4_MUX=1
sCH5_IN_freq=156.25e6
sCH5_MUX=1
sCH6_IN_freq=100e6
sCH6_MUX=1
sCH7_IN_freq=100e6
sCH7_MUX=1
sDPLL_DCO_STEP=0.01
sDPLL_DCO_STEP_ACT=0.00999960507331635
sDPLL_HISTCNT_calc=5.13 ms
sDPLL_HISTDLY_calc=2.57 ms
sDPLL_LBW=60
sDPLL_LBW_ACCURACY=5
sDPLL_LBW_ACT=60.29
sDPLL_LOCK_ACCURACY_PPM=1
sDPLL_LOCK_AVG=2
sDPLL_LOCK_PPM=1
sDPLL_PEAK=0.1
sDPLL_REF_COMMON_DIV=1000000000
sDPLL_TDC_freq=398.843594 kHz
sDPLL_TMEAS_LOCK_calc=19.20 ms
sDPLL_TMEAS_UNLK_calc=3.84 ms
sDPLL_UNLK_ACCURACY_PPM=5
sDPLL_UNLK_AVG=2
sDPLL_UNLK_PPM=10
sMAX_TDC_freq=400000
sMAX_TDC_simple=0
sMAX_XO_PPM=50
sPRIREF_ACCURACY_PPM=10
sPRIREF_AVG_COUNT=2
sPRIREF_EARLY_MARGIN=0
sPRIREF_EARLY_calc=6.40 ns
sPRIREF_LATE=0
sPRIREF_LATE_MARGIN=1
sPRIREF_LATE_calc=17.60 ns
sPRIREF_PH_VALID_calc=n/a; PRIREF > 2 kHz
sPRIREF_PPM_INVALID=26
sPRIREF_PPM_TIMER=4.17 ms
sPRIREF_PPM_VALID=20
sPRIREF_freq=80566406
sSECREF_ACCURACY_PPM=10
sSECREF_AVG_COUNT=2
sSECREF_EARLY_MARGIN=0
sSECREF_EARLY_calc=6.40 ns
sSECREF_LATE=0
sSECREF_LATE_MARGIN=1
sSECREF_LATE_calc=17.60 ns
sSECREF_PH_VALID_calc=n/a; SECREF > 2 kHz
sSECREF_PPM_INVALID=26
sSECREF_PPM_TIMER=4.17 ms
sSECREF_PPM_VALID=20
sSECREF_freq=80566406
sVCO1_freq=156.25e6*16*1
sVCO2_freq=0
sXO_freq=48.00e6
NVM_ERASE_PROG=0
REGCOMMIT_PG=0
bEXPORTEEPROMFILE=Export GUI Map --> EEPROM File
bIMPORTEEPROMFILE=(1b) Import EEPROM File --> GUI Map
bLoadDefaultEEPROMImageToGUIMap=(1c) Load Default EEPROM Image --> GUI Map
bLoadPage_from_GUIMap_to_GUI_Registers=Load GUI Map PAGE --> Register
bPROGRAMEEPROM=(3) Program EEPROM <-- SRAM
bREADBACKEEPROM=Read All EEPROM --> GUI Map
bREADBACKROM=Read All ROM --> GUI Map
bREADBACKSRAM=Read All SRAM --> GUI Map
bREG2EE=(1a) Commit Registers --> SRAM PAGE/GUI Map
cbEESLAVEADR=0
mtc_EEPROMdump=
mtc_USERNOTES=Enter User Notes
tc_DESIGNNAME=Enter Design Name
PLL1_DEN=1099511627776
PLL1_PFD_freq=24
VCO1_freq=2500
XO_freq=48
PLL2_DEN=16777216
PLL2_PFD_freq=138.888888888889
VCO1_freq=2500
VCO2_freq=5500
XO_freq=48
PRIREF_VALSTAT=1
SECREF_VALSTAT=1
bClearAllFlagStickyStatus=Clear All Flags
bReadStatus=Read Status
MUTE_DPLL_FRLOCK=0
OUT0_freq=156.25
OUT1_freq=156.25
OUT2_freq=156.25
OUT3_freq=156.25
OUT4_freq=156.25
OUT5_freq=156.25
OUT6_freq=100
OUT7_freq=100
PLL2PDIV1_freq=0
PLL2PDIV2_freq=0
VCO1_freq=2500
VCO2_freq=5500
sOUT7_DIV=25
PLL1_BAW_CAPDAC=0
bFindAddressBtn=Find I2C Addr
i2cAddr=0
OSCIN_DBLR_EN=0
OSCIN_RDIV=1
OSCIN_DBLR_EN=0
OSCIN_RDIV=1
OSCIN_DBLR_EN=0
OSCIN_RDIV=1
OSCIN_DBLR_EN=0
OSCIN_DBLR_EN=0
OSCIN_RDIV=1

0 Timothy T over 1 year ago in reply to Vaison Xia

TI__Mastermind 28540 points

Ok thanks, I've got your configs and am reviewing. I expect to have another update for you this week.

73,
Timothy

0 Vaison Xia over 1 year ago in reply to Timothy T

Prodigy 10 points

Hi, Timothy,

Thanks for your help! The XO input of LMK05318 on my board 48MHz, 25PPM.

The center frequence to PRIREF and SECREF per our calculation is 80566406Hz (from our chip output). Would you make a tcs file for 80566406Hz 50ppm range to have LMK05318 DPLL lock? Thanks!

Vaison

0 Timothy T over 1 year ago in reply to Vaison Xia

TI__Mastermind 28540 points

Hi,

I'll check into it...

73,
Timothy

0 Vaison Xia over 1 year ago in reply to Timothy T

Prodigy 10 points

Hi, Timothy,

Any update? Our Intel ref board uses LMK05318. I hope you can help resolve this issue and our customers will be following our ref design.

I did more test on my Intel ref board and found the input range to the registers via USB2ANY tool for PRIREF between 80566400-80553640=12,760HZ can make LMK05318 DPLL lock. But it cannot achieve my goal to have 80566406 Hz (which is center frequence ) to lock or its +/-50 ppm to lock.

Would you help ? Thanks!

Vaison

0 Timothy T over 1 year ago in reply to Vaison Xia

TI__Mastermind 28540 points

Yes, I will update this week.

0 Riley Nguyen over 1 year ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

The LMK05318 TICS Pro doesn't show DPLL calculation, I would recommend to use LMK05318B TICS Pro so that you can see DPLL calculation is updated when changing PRIREF.

On the wizard page, make sure to set "Backward Compatible" so it can work with the non-B device.

When loading your non-working config file, the DPLL shows 0 for both numerator and denominator; thus, calculates incorrect BAW VCO frequency. The correct num/den below would properly update the BAW VCO to 2500 MHz.

This is the .tcs file with updated calculation for 80566406 Hz: 80566406Hz_updated_DPLL_calculation.tcs

-Riley

0 Vaison Xia over 1 year ago in reply to Riley Nguyen

Prodigy 10 points

Hi, Riley,

Thanks for your update and reply.

1.I updated TICS Pro to v 1.7.5.7 which can support LMK05318B. I chose "Backward Compatible" at the beginning. I input all my requirement , and ran, but DPLL was not locked yet. Please see "80566406Hz using new TICS PRO backward compatible.tcs" below. Would you check? Thanks!

2. On the other debug, I also loaded your 80566406Hz_updated_DPLL_calculation.tcs, and then clicked ''write all registers", and then read status, the DPLL was not locked yet.

3. Do I have to use LMK05318B to fix the issue? If yes, can I apply one LMK05318B example from your TI sales team (if yes, can you tell me his/her e-mail address)?

Thanks for your help!

Vaison

----80566406Hz using new TICS PRO backward compatible.tcs --

[SETUP]
ADDRESS=888
CLOCK=8
DATA=4
LE=2
PART=LMK05318B
IFACE=I2C
ADDRESS_I2C=0x64
INTERFACE_SPEED=100

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[FLEX]
CH0_PREDRIVER=0
CH1_PREDRIVER=0
CH2_PREDRIVER=0
CH3_PREDRIVER=0
CH4_PREDRIVER=0
CH5_PREDRIVER=0
CH6_PREDRIVER=0
CH7_PREDRIVER=0
DPLL_REF_LOOPCTL_CHG_QUANT_INTG=0
DPLL_REF_MASHSEED=0
DPLL_REF_UNLOCKDET_CNTSTRT=0
DPLL_REF_UNLOCKDET_VCO_CNTSTRT=0
MUTE_DPLL_FRLOCK=0
OUT0_freq=312.5 MHz
OUT1_freq=312.5 MHz
OUT2_freq=312.5 MHz
OUT3_freq=312.5 MHz
OUT4_freq=312.5 MHz
OUT5_freq=312.5 MHz
OUT6_freq=200.0 MHz
OUT7_freq=200.0 MHz
PLL1_BAW_CAPDAC=0
PLL1_CP_TRIM=0
PLL1_VCBO_VAR2CON=0
PRIREFBUFGAIN=0
SECREFBUFGAIN=0
VCO1_freq=2498.35627318812
VCO2_freq=0
XO_freq=48
bFindAddressBtn=Find I2C Addr
i2cAddr=0
sTDC_freq=398.8436 kHz
btn_page0_next=NEXT>
combo_backward_compatible=1
combo_dpll_mode=0
combo_ref_freq=1
matlab_runtime_url=www.mathworks.com/.../matlab-runtime.html
btn_page1_back=<BACK
btn_page1_next=NEXT>
btn_xo_show_instructions=Show Instructions
sXO_freq=48.00e6
s_wizard_XO_message_box=XO frequency set successfully!\n\nInteger boundary spur = 4.0 MHz\n\nXO R divider = 1\nXO doubler is disabled\nPFD frequency = 48.0 MHz
OUT0_freq=312.5 MHz
OUT1_freq=312.5 MHz
OUT2_freq=312.5 MHz
OUT3_freq=312.5 MHz
OUT4_freq=312.5 MHz
OUT5_freq=312.5 MHz
OUT6_freq=200.0 MHz
OUT7_freq=200.0 MHz
PLL1_RDIV_StaticText=PLL2 R divider (two stages)
bCALC_FREQPLAN=Calculate Frequency Plan
btn_freq_plan_show_instructions=Show Instructions
btn_frequency_plan_apply_solution=Apply selected solution
btn_page2_back=<BACK
btn_page2_next=NEXT>
cb_allow_PLL2_prescaler_of_2=0
cb_manual_override_pll2_rdiv=0
sCH0_1_IN_freq=156.25e6
sCH0_1_MUX=1
sCH2_3_IN_freq=156.25e6
sCH2_3_MUX=1
sCH4_IN_freq=156.25e6
sCH4_MUX=1
sCH5_IN_freq=156.25e6
sCH5_MUX=1
sCH6_IN_freq=100e6
sCH6_MUX=1
sCH7_IN_freq=100e6
sCH7_MUX=1
s_wizard_freqplan_message_box=Frequency plan completed!\n\nSelected frequency plan:\n\nVCO1 frequency = 2500.0 MHz\nVCO2 frequency = 0.0 MHz\n\nAPLL1 settings:\n\nPFD freq = 48000000 Hz\nN divider = 52\nNumerator = 91625968981\nDenominator = 1099511627776\nPost divider = 1
table_frequency_plan_pll1=0
table_frequency_plan_pll2=0
btn_page3_back=<BACK
btn_page3_next=NEXT>
btn_refclk_show_instructions=Show Instructions
cb_enable_PRIREF=1
cb_enable_SECREF=1
combo_PRIREF_BUF_TYPE=1
combo_SECREF_BUF_TYPE=1
combo_ref_priority=0
refclk_pin_select=
sPRIREF_freq=80566406
sSECREF_freq=80566406
s_wizard_refclk_message_box=INSTRUCTIONS:\n\n1. Enable or disable PRIREF and SECREF as needed. If DPLL is not used, then disable both references and skip this page.\n\n2. Type the frequencies of PRIREF and / or SECREF in Hz. Example frequency formats:\n\n1\n25e6\n100e6 / 3\n\n3. Select interface type. AC or DC buffer is auto-seletected based on reference frequency. If reference frequency is below 5 MHz, then use DC buffer. Otherwise, use AC buffer. To select interface types for AC buffer, refer to the 'Interface Type Selection Tips' in the XO wizard page. The same can be applied to PRIREF and SECREF.\n\n4. Select the input switching mode. The input switching mode is auto-seletected based on the states of PRIREF and SECREF enable. When both references are enabled, then Auto non-revertive is selected. If only one reference is enabled, then manual holdover is selected. However, it is highly recommended to read through the 'Input Switching Mode Selection Guide' in this wizard page and make the decision.\n\n5. If manual fallback or manual holdover is selected, then choose between manually select by register and manually select by REFSEL pin.
btn_page4_back=<BACK
btn_page4_next=NEXT>
btn_ref_validation_show_instructions=Show Instructions
sPRIREF_ACCURACY_PPM=10
sPRIREF_AVG_COUNT=2
sPRIREF_EARLY_MARGIN=0
sPRIREF_EARLY_calc=6.01 ns
sPRIREF_LATE=0
sPRIREF_LATE_MARGIN=1
sPRIREF_LATE_calc=5.19 ns
sPRIREF_PH_VALID_calc=n/a
sPRIREF_PPM_INVALID=26
sPRIREF_PPM_TIMER=n/a
sPRIREF_PPM_VALID=20
sSECREF_ACCURACY_PPM=10
sSECREF_AVG_COUNT=2
sSECREF_EARLY_MARGIN=0
sSECREF_EARLY_calc=6.01 ns
sSECREF_LATE=0
sSECREF_LATE_MARGIN=1
sSECREF_LATE_calc=5.19 ns
sSECREF_PH_VALID_calc=n/a
sSECREF_PPM_INVALID=26
sSECREF_PPM_TIMER=n/a
sSECREF_PPM_VALID=20
s_wizard_reference_validation_message_box=INSTRUCTIONS:\n\nIf DPLL is disabled, then skip this page. All reference validation methods have been enabled or disabled automatically based on reference frequency and interface type. However, it is highly recommended to read through the instructions and loose or tighten the thresholds according to application needs.\n\nFrequency detection and early / late window detection are only valid for reference frequencies >= 2 kHz. 1-pps phase detector is only valid for reference frequencies < 2 kHz. For 1-pps input, only enable the 1-pps phase detector and disable all other detectors.\n\n1. Validation timer. The reference must stay valid for 'validation timer' amount of time before it's considered valid. It is recommended to set the validation timer to more than twice of the total reference validation measurement time. The frequency detection measurement time is displayed on the wizard. Measurement time of amplitude detection, early / late clock detection as well as 1-pps phase detection is roughly one cycle of reference clock. Therefore, if the reference frequency is >= 2 kHz, total measurement time is approximately the frequency detection measurement time. If the reference frequency is < 2 kHz, total measuremnet time is approximately 1 cycle of reference clock.\n\n2. Amplitude detector. There are two modes: amplitude detector mode and CMOS slew rate detector mode. In amplitude detector mode, the reference is considered valid if the signal swing is higher than the selected threshold. In CMOS slew rate detector mode, the detection method can be either slew rate detection or VIH / VIL detection. For slew rate detection, the input slew rate must be faster than 0.2 V/ns. For VIH / VIL detection, the input high level must be above 1.8 V and the low level must be below 0.6 V. The amplitude detection mode cannot be used for reference frequencies less than 5 MHz. If the reference frequency is above 5 MHz, then amplitude detection mode is recommended for differential input and the CMOS slew rate detection mode is recommended for single-ended input. If the input swing is too low (for example, the LVDS voltage swing is 400 mV, very marginal compared to the mininum threshold of amplitude detection mode), then amplitude detector can be disabled.\n\n3. Frequency detector. This detector is only valid for PRIREF / SECREF frequencies >= 2 kHz. Frequency detection needs 4 parameters: valid threshold in ppm, invalid threshold in ppm, accuracy in ppm and average count. The PRIREF or SECREF is considered valid if the frequency error between PRIREF / SECREF and XO is within the valid threshold. While it's frequency valid, it's considered as frequency invalid if the frequency error exceeds the invalid threshold. The accuracy in ppm indicates how accurate the valid and invalid threshold can be. In other words, this is the resolution of valid and invalid threshold counters. The minimum average count is 2. Keep it as 2 unless the reference clock has too much wander and the DPLL loop bandwidth is too narrow. In that case, raise the average count to no more than 10. As mentioned, the '0-error' reference for frequency detection is the XO. In reality, of course, the XO frequency is not '0-error'. Therefore, the valid and invalid thresholds must take the XO ppm error into account. The minimum valid threshold should be max XO frequency error + max PRIREF / SECREF frequency error + accuracy in ppm. The minimum invalid threshold should be valid threshold + accuracy in ppm.\n\n4. Early and late clock window detector. This detector is only valid for PRIREF / SECREF frequencies >= 2 kHz. 3 parameters are needed: early counter, late counter and number of missing clocks. After setting early and late counters, the T_early and T_late are calculated accordingly. As shown in the timing diagram, the PRIREF / SECREF is considered valid if its next clock edge falls within ideal next edge - T_early and ideal next edge + T_late. Setting the number of missing clocks to x is equivalent to adding x * reference_clock_period to T_late. So the number of missing clocks is typically set to 0 unless gapped clock needs to be supported. The early and late clock detector uses divided down BAW VCO frequency as its '0-error' reference. However, since this is a very coarse detection method (resolution of T_early and T_late counter is roughly 1.6 ns), the ppm error of the BAW VCO itself is not of concern.\n\n5. 1-pps phase detector. This detector is only valid for PRIREF / SECREF frequencies < 2 kHz. T_jitter is auto-calculated according to the phase detector counter. As shown in the timing diagram, the PRIREF / SECREF is considered valid if the next clock edge falls within ideal next edge - T_jitter and ideal next edge + T_jitter. Note that the '0-error' clock reference for 1-pps phase detector is the XO, so T_jitter must be greater than the sum of: (1) XO phase error accumulated through one PRIREF / SECREF clock period (for example, 1 second for 1-pps input). This includes the phase error caused by frequency inaccuracy, accumulated jitter as well as wander. (2) The max period jitter of PRIREF / SECREF. Therefore, low frequency and high stability XO is recommended for 1-pps input. This is because for XOs with the same frequency stability, the one with the lower frequency accumulates less phase error over fixed period of time. 12.8 MHz TCXO / OCXO is recommended for 1-pps input.
DPLL_VCO_freq=2498.35627318812
bRUN_SCRIPT=Run Script
btn_dpll_show_instructions=Show Instructions
btn_page5_back=<BACK
btn_page5_next=NEXT>
btn_restore_dpll_reg=Restore Calculated DPLL Settings
cb_show_dpll_registers=1
combo_disable_fastlock=0
combo_set_max_tdc_freq=1
combo_switching_method=0
sDPLL_LBW=60
sDPLL_LBW_ACT=60.94
sDPLL_PEAK=0.1
sDPLL_PEAK_ERROR=1
sMAX_TDC_freq=400000
sPRIREF_freq_display=80.5664 MHz
sSECREF_freq_display=80.5664 MHz
sTDC_freq=398.8436 kHz
s_wizard_dpll_message_box=Written DPLL registers:\n\nDPLL_REF_DEN = 0\nDPLL_REF_NUM = 0\nDPLL_REF_DECIMATION = 0\nDPLL_REF_DITHER = 0\nDPLL_REF_FB_PRE_DIV = 1\nDPLL_REF_FB_DIV = 1044\nDPLL_REF_FILT_GAIN = 0\nDPLL_REF_FILT_GAIN_FL1 = 0\nDPLL_REF_FILT_GAIN_FL2 = 0\nDPLL_REF_FILT_SCALAR = 870\nDPLL_REF_LOOP_GAIN = 16\nDPLL_REF_LOOP_GAIN_FL1 = 15\nDPLL_REF_LOOP_GAIN_FL2 = 16\nDPLL_REF_LPF0_GAIN = 7\nDPLL_REF_LPF0_GAIN_FL1 = 8\nDPLL_REF_LPF0_GAIN_FL2 = 7\nDPLL_REF_LPF1_GAIN = 6\nDPLL_REF_LPF1_GAIN_FL1 = 10\nDPLL_REF_LPF1_GAIN_FL2 = 6\nDPLL_REF_QUANT = 3\nDPLL_REF_QUANT_FL1 = 5\nDPLL_REF_QUANT_FL2 = 3\nDPLL_REF_LOOPFILT_CLK_DIV = 10\nDPLL_REF_LPF0_GAIN2_FL = 30\nDPLL_REF_LPF1_GAIN2_FL = 30\nDPLL_REF_TMR_FL1 = 621\nDPLL_REF_TMR_FL2 = 47\nDPLL_REF_MASHSEED = 0\nDPLL_REF_ORDER = 3\nDPLL_PRIREF_RDIV = 202\nDPLL_SECREF_RDIV = 202\nPLL1_ORDER = 3\nPLL1_NDIV = 104\nPLL1_NUM = 183251937963\nDPLL_REF_CYCSLIP_OFFSET = 12536\nDPLL_REF_TDC_HI_SPD_MODE = 0\nDPLL_TDC_REF_DLY_GEN_EN = 1\nRAMP_CNTR_EN = 1\nDPLL_TDC_DLY_STEPSIZE2X_EN = 1\nDPLL_REF_AVOID_SLIP = 1\nDPLL_FASTLOCK_ALWAYS = 0\nDPLL_SWITCHOVER_ALWAYS = 1\n
BAW_LOCK_PPM_THRESH=5
BAW_UNLK_PPM_THRESH=10
DPLL_PL_LOCK_calc=235.40 ps
DPLL_PL_UNLK_calc=7.53 ns
btn_baw_lock_detect_default=Set Default
btn_dpll2_show_instructions=Show Instructions
btn_dpll_freq_lock_detect_default=Set Default
btn_history_recommend=Min Values Required
btn_page6_back=<BACK
btn_page6_next=NEXT>
btn_ph_threshold_recommend=Recommended
sBAW_LOCK_ACCURACY_PPM=1
sBAW_LOCK_AVG=2
sBAW_TMEAS_LOCK_calc=19.2000 ms
sDPLL_HISTCNT_calc=657.26 ms
sDPLL_HISTDLY_calc=115.53 ms
sDPLL_LOCK_ACCURACY_PPM=1
sDPLL_LOCK_AVG=10
sDPLL_LOCK_PPM=1
sDPLL_PL_MEAS_TIME=16.41 ms
sDPLL_TMEAS_LOCK_calc=96.0000 ms
sDPLL_UNLK_PPM=10
s_wizard_dpll2_message_box=INSTRUCTIONS:\n\nAll lock detect settings are set to either default or recommended values after the DPLL script is run. Still, it is highly recommended to go through the instructions and make the adjustments.\n\n1. BAW frequency lock detect. Disable this if DPLL is enabled. This detector is only useful if the DPLL is disabled and the device works in free-running mode. Enter lock threshold in ppm, unlock threshold in ppm, average count (min value = 2) and accuracy in ppm. The BAW (VCO1) is considered to be locked if the frequency error between the BAW and the XO is within lock threshold. Once the BAW is locked, it's considered to be unlocked if the frequency error exceeds the unlock threshold. The step size of lock and unlock threshold in ppm = accuracy / average. If there's no specific requirement for BAW lock detect, click 'Set Default'.\n\n2. DPLL frequency lock detect. Enter lock and unlock thresholds in ppm, average count (min value = 2) as well as accuracy in ppm. The DPLL is considered to be frequency locked if the frequency error between the VCO1 and the references is within the lock threshold. While the DPLL is frequency locked, it's considered to be frequency unlocked if the frequency error exceeds the unlock threshold. The step size of lock and unlock threshold = accuracy / average. If there's no specific requirement for DPLL frequency lock detect, click 'Set Default'.\n\n3. DPLL phase lock detect. Set lock and unlock threshold counters. The actual lock and unlock thresholds in second are then calculated accordingly. The DPLL is considered as phase locked if the phase difference between the two inputs of TDC (divided reference and divided VCO1) is within the lock threshold. While the DPLL is phase locked, it's considered as phase unlocked if the phase difference exceeds the unlock threshold. Use recommended values for this. The lock and unlock counters should not be manually set, and they are only used for engineering debugging purposes.\n\n4. Tuning word history. This block sets the tuning word history for holdover. Set history counter and delay counter. The averaging time and delay time are then auto-calculated. Refer to datasheet section '9.3.7.4 Tuning Word History' for details. If there's no specific requirement for holdover tuning word, click 'Min Values Required'. This makes sure that the delay time is more than 8 times of the reference frequency validation measurement time, and that the averaging time is longer than the delay time.
btn_page7_back=<BACK
PLL1_24b_DEN=11184811
PLL1_24b_NUM=9185962
PLL1_DEN=1099511627776
PLL1_PFD_freq=48
VCO1_freq=2498.35627318812
XO_freq=48
PLL2_DEN_fixed=16777216
PLL2_PFD_freq=277.7777777778
VCO1_freq=2498.35627318812
VCO2_freq=0
XO_freq=48
MUTE_DPLL_FRLOCK=0
OUT0_freq=312.5 MHz
OUT1_freq=312.5 MHz
OUT2_freq=312.5 MHz
OUT3_freq=312.5 MHz
OUT4_freq=312.5 MHz
OUT5_freq=312.5 MHz
OUT6_freq=200.0 MHz
OUT7_freq=200.0 MHz
PLL2PDIV1_freq=0
PLL2PDIV2_freq=0
VCO1_freq=2498.35627318812
VCO2_freq=0
sOUT7_DIV=25
AbsDCO_ppb_error=0.01
DPLL_DCO_FREQ_PPB_ACT=657490.724752475
DPLL_DCO_STEP_ACT=0.0190642886394522
DPLL_REF_NUM_calculated=0
bDPLL_FDECR=Decrement
bDPLL_FINCR=Increment
bResetNumerator0ppb=Reload Original DPLL Numerator
cbDCO_MODE=1
sDPLL_DCO_STEP=0.01
sSYNC_PHASE_OFFSET=
bClearAllFlagStickyStatus=Clear All Flags
bReadStatus=Read Status
ADDR_10=0
ADDR_11=0
ADDR_249=0
ADDR_250=0
ADDR_251=0
ADDR_252=0
REGCOMMIT_PG=0
bEXPORTEEPROMFILE=Export GUI Map --> EEPROM File
bIMPORTEEPROMFILE=(1b) Import EEPROM File --> GUI Map
bLoadDefaultEEPROMImageToGUIMap=(1c) Load Default EEPROM Image --> GUI Map
bLoadPage_from_GUIMap_to_GUI_Registers=Load GUI Map PAGE --> Register
bPROGRAMEEPROM=(3) Program EEPROM <-- SRAM
bREADBACKEEPROM=Read All EEPROM --> GUI Map
bREADBACKROM=Read All ROM --> GUI Map
bREADBACKSRAM=Read All SRAM --> GUI Map
bREG2EE=(1a) Commit Registers --> SRAM PAGE/GUI Map
bUpdate_ExtraEEPROM_Bytes=Read Extra\nEEPROM Bytes
cbEESLAVEADR=0
cbWrite_ADR10=0
cbWrite_ADR11=0
mtc_EEPROMdump=
mtc_USERNOTES=Enter User Notes
tc_DESIGNNAME=Enter Design Name

-----

0 Riley Nguyen over 1 year ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

The recommendation to use TICS PRO of LMK05318B is that you would be able to see DPLL calculation on the software. You can use the B-version software to configure with the non-B part and set to "Backward compatible".

I was able to get DPLL locked with the config I shared. When checking status, did you see PRIREF/SECREF inputs valid?

-Riley

0 Riley Nguyen over 1 year ago in reply to Vaison Xia

TI__Intellectual 1435 points

BTW, although there is no upload button for the file, you can actually drag and drop the file in the reply box and it would be upload among with your comment.

-Riley

0 Vaison Xia over 1 year ago in reply to Riley Nguyen

Prodigy 10 points

Hi, Riley,

Thanks for your help!

When checking status, I did see inputs valid.

After I clicked “Soft-reset chip” in the top menu of TICS PRO, and I loaded again your tcs file, then I saw

the DPLL lock on 80566406 Hz PRIREF setting. Thanks!

Then I changed the input frequence value of PRIREF on TICS PRO (others same as your tcs file cfg), to test the frequence range which can be locked by LMK05318 DPLL. The result is :

80566244Hz (-2 ppm from 80566406Hz ) to 80566808Hz (almost +5ppm from 80566406Hz ) can be locked by LMK05318 DPLL.

It seems the total 7ppm (2+5) is too narrow. Would you confirm it is as you expected for LMK05318?

Since 80566406Hz is our theoretical center frequence and it is from our Ethernet Switch SerDes RX syncE recover clock output, and the local clock source for the Ethernet switch is 156.25M +/-20ppm (Ethernet standard), we need wider range (greater than 7 ppm) of PRIREF input value to be locked by LMK05318 DPLL.

Is it possible to make 40 ppm range (+/-20 ppm to center frequence 80566406Hz) to be locked by LMK05318 DPLL? If that is possible, can you help and send me the tcs file?

(I tried to enable Frequence detect threshold on TICS PRO, but it made things worse which is the center frequence 80566406Hz even cannot be locked by by LMK05318 DPLL. )

Thanks so much!

Vaison

0 Riley Nguyen over 1 year ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

The Frequency Detect Threshold would also account for XO frequency error, so if it is enabled, the threshold should also be increased to validate the ppm error for both PRIREF/SECREF + XO.

By default, the config has this disabled so it would check PRIREF/SECREF only.

I would need to test sweeping +/- 40 ppm on the reference input and get back on this.

-Riley

0 Vaison Xia over 1 year ago in reply to Riley Nguyen

Prodigy 10 points

Hi, Riley,

Any update on test sweeping +/- 40 ppm on the reference input from your side? Thanks!

Vaison from Intel

0 Riley Nguyen over 1 year ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

I'm looking into scripts that do frequency sweeping on the input so I can check this config.

-Riley

0 Riley Nguyen over 1 year ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

I have checked shifting +/- 20 ppm and +/- 40 ppm. I can see the output stays in lock with the shifting reference. Please see this attachment: LMK05318B DPLL REF Lock Testing.pdf

One notice that, when changing input reference, you just need to change the input only (from SigGen, etc.), no need to adjust it from TICS Pro software. The DUT will detect the change in the input reference and adjust the output to follow this change and stay in lock with PRIREF/SECREF. Let me know if this helps.

-Riley

0 Riley Nguyen over 1 year ago in reply to Riley Nguyen

TI__Intellectual 1435 points

Also, your config have all the outputs generated from APLL1 (BAW VCO 2500 MHz). The BAW VCO has +/- 100 ppm, so the outputs generated from this BAW VCO would follow the drift of the input reference (PRIREF/SECREF) up to +/- 100 ppm in this case.

-Riley

0 Vaison Xia over 1 year ago in reply to Riley Nguyen

Prodigy 10 points

Hi, Riley,

Thanks for your hard work on this test and very good slides to show your test result.

Can you send me the .tcs file you were testing for your test result slides? Thanks!

I understood no need to adjust it from TICS Pro software.

Vaison

0 Riley Nguyen over 1 year ago in reply to Vaison Xia

TI__Intellectual 1435 points

Vaison,

I use the same config file that I shared to you before: 3480.80566406Hz_updated_DPLL_calculation.tcs

There is nothing change in the config as no adjustment made to the input reference frequency on TICS Pro.

-Riley

0 Vaison Xia over 1 year ago in reply to Vaison Xia

Prodigy 10 points

Hi, Riley,

I am using LMK05318 A0 chip, instead of B0 chip. Your test result is on LMK05318 B0. Does your test result also apply to LMK05318 A0 chip? Thanks!

Vaison

0 Riley Nguyen over 1 year ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

One difference on the LMK05318 non-B is that its BAW VCO has +/- 50 ppm instead of +/- 100 ppm in B-version. But +/- 50 ppm range would cover that you need in your test with non-B version.

Regard the performance of the LMK05318 non-B version, that would be no difference than the above test result. You would use the similar test procedure to shift the input frequency range.

Riley

0 Vaison Xia over 1 year ago in reply to Riley Nguyen

Prodigy 10 points

Hi, Riley,

Thanks for your explanation!

I will run some test on my boards. Thanks!

Vaison

0 Vaison Xia over 1 year ago in reply to Vaison Xia

Prodigy 10 points

Hi, Riley,

I discussed with our Intel AE team for your test result slides.

We understood that is for testing shift/drift range.

But what we want mostly is pull in range.

Would you help to do the following tests to find out the pull in range? Thanks!

Power off and power on the LMK05318 board, config LMK05318 for PRIREF/SECREF center frequency = 80566406 Hz.

Then set SigGen to output 80563183Hz (which is 80566406 Hz -40 ppm ) to PRIREF/SCREF, to see if LMK05318 can lock or not.

Power off and power on the LMK05318 board, config LMK05318 for PRIREF/SECREF center frequency = 80566406 Hz.

then set SigGen to output 80569629 Hz (which is 80566406 Hz +40 ppm ) to PRIREF/SCREF, to see if LMK05318 can lock or not.

Power off and power on the LMK05318 board, config LMK05318 for PRIREF/SECREF center frequency = 80566406 Hz.

Then set SigGen to output 80564795 Hz (which is 80566406 Hz -20 ppm ) to PRIREF/SCREF, to see if LMK05318 can lock or not.

Power off and power on the LMK05318 board, config LMK05318 for PRIREF/SECREF center frequency = 80566406 Hz.

then set SigGen to output 80568017 Hz (which is 80566406 Hz +20 ppm ) to PRIREF/SCREF, to see if LMK05318 can lock or not.

Vaison

0 Riley Nguyen over 1 year ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

The pull in range is also +/- 50 ppm max on LMK05318 due to the BAW VCO range that used in your config.

I have tested powering the device off/one then loading the config with PRIREF/SECREF at 80566406 Hz while SigGen to PRIREF/SECREF set at +/- 20 ppm and +/- 40 ppm, the device does lock to the shifted reference frequencies. Note that after powering the device, make sure to "Write All Regs" and "Soft-reset Chip" to load the config again.

-Riley

0 Vaison Xia over 1 year ago in reply to Riley Nguyen

Prodigy 10 points

Riley,

Thanks for your reply and test again!

I will discuss your feedback with our AE team and might run some test. Thanks!

Vaison

0 Vaison Xia 11 months ago in reply to Vaison Xia

Prodigy 10 points

Hi, Riley,

I tested 80566406Hz with your tcs file and the LMK05318 DPLL was locked. Thanks for your help!

Now I moved to test other freq output from our Intel Ethernet switch. I tested LMK05318 PRIREF and SECREF with input 40283203Hz.

I used the same tcs file from you (3480.80566406Hz_updated_DPLL_calculation.tcs), and then changed PRIREF and SECREF from 80566406Hz to 40283203Hz in Wizard page step 3; then clicked "Run script " in step 5 and waited it was done, then "Write All Regs" or "Soft-reset Chip" "Write All Regs". But the DPLL was not locked : LOFL_DPLL is flagged

Our Ethernet switch outputs clock 40283203Hz correctly.

I attached my tcs file. Would you help check the file if there is anything wrong ? If you can generate a tcs file , I can have a try.PRIREF 40283203Hz not lock.tcs

Thanks!

(In order to run DPLL calculation script,I have installed Matlab runtime R2015b (9.0) 64 bit)

Vaison

0 Riley Nguyen 11 months ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

What is the DPLL calculation (N divider, num and den values) when you use 40283203Hz for input ref?

-Riley

0 Vaison Xia 11 months ago in reply to Riley Nguyen

Prodigy 10 points

Hi, Riley,

Thanks for your help! In my Wizard step 2: I clicked "Apply selected solution", then click "calculate frequence plan" , below is the information. Thanks!

Step 3 input 40283203Hz for PRIREF and SECREF , Step 5 click"run script ", then "Write All Regs" or "Soft-reset Chip" "Write All Regs". But the DPLL was not locked : LOFL_DPLL is flagged (read status: LOFL_DPLL is flagged.)

----

Frequency plan completed!

Selected frequency plan:

VCO1 frequency = 2500.0 MHz
VCO2 frequency = 0.0 MHz

APLL1 settings:

PFD freq = 24000000 Hz
N divider = 104
Numerator = 183251937963
Denominator = 1099511627776
Post divider = 1

------

0 Riley Nguyen 11 months ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

I would be able to check it in the next few days. and get back to you.

-Riley

0 Riley Nguyen 11 months ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

Sorry for the delay response.

Vaison Xia said:
Frequency plan completed!

Selected frequency plan:

VCO1 frequency = 2500.0 MHz
VCO2 frequency = 0.0 MHz

APLL1 settings:

PFD freq = 24000000 Hz
N divider = 104
Numerator = 183251937963
Denominator = 1099511627776
Post divider = 1

This message is from APLL page.

I've checked your new config and it's the similar error where DPLL calculation shows 0 on Num and Den. I have updated the calculation and checked it locked: PRIREF 40283203Hz lock with updated DPLL calculation.tcs

Since the new REF frequency is 1/2 of the previous REF frequency, you would notice Num and Den of DPLL calculation are actually the same.

-Riley

0 Vaison Xia 11 months ago in reply to Riley Nguyen

Prodigy 10 points

Hi, Riley,

Thanks for your checking and the updated tcs file!

Yes, I saw Num and Den of DPLL are 0 in my step 5 (Set DPLL). I thought it was calculated automatically.

I will also test other center frequency. Would you tell me how to avoid that error ? So that I can rerun the Wizard for other center frequency and I hope I don’t waste your time for same error again.

I tried these methods in the Wizard:

Method 1: After changed the PRIREF and SECREF frequency value to 40283203Hz in step 2(Set DPL references), I clicked “run script” in Step 5 (Set DPLL), and waited it is done. When it was done , Num and Den for the Fractional N divider were still 0. Why?

Method 2: Loaded your “PRIREF 40283203Hz lock with updated DPLL calculation.tcs” file, and Num and Den for the Fractional N divider are correct as you, then I did soft-reset chip, write all regs, but the DPLL was not locked.

Method 3 : Loaded your “PRIREF 40283203Hz lock with updated DPLL calculation.tcs” file,then I clicked “run script” in Step 5 (Set DPLL). When it was done , Num and Den for the Fractional N divider changed to 0. Why?

I think something wrong in the Wizard. Is it related to Matlab version I installed (R2015b(9.0) 64-bit?

Please correct me. Thanks!

Vaison

0 Evan Su 11 months ago in reply to Vaison Xia

TI__Genius 9700 points

Hi Vaison,

The MATLAB version should be correct. I would expect the "Run Script" button to automatically update the Num and Den values once it is done, sounds like you are encountering a strange bug. Are the other DPLL settings being updated at all once "Run Script" is finished?

Best,

Evan Su

0 Vaison Xia 11 months ago in reply to Evan Su

Prodigy 10 points

Hi, Evan and Riley,

Thanks for your help! I uploaded 3 snapshots before, when and after Run script. It seems something wrong on my TICS Pro. But I don't know what the problem is and how to fix it. I appreciate you can help. Thanks!

Vaison

0 Evan Su 11 months ago in reply to Vaison Xia

TI__Genius 9700 points

Hi Vaison,

I see what you mean, the initial configuration you loaded has the correct nonzero numerator/denominator but after running the script they get cleared to 0/0 for some reason. The rest of the PLL registers seem correct.

The only clue I see is the warning in the CMD window, "Inputs contain values larger than the largest consecutive flint. Result may be inaccurate", which is happening inside of the function that updates the numerator and denominator. I will wait to see if Riley has any ideas, if not we should contact our software expert.

Best,

Evan Su

0 Vaison Xia 10 months ago in reply to Evan Su

Prodigy 10 points

Thanks, Evan.

Hi, Riley,

Any idea on how to resolve this software issue of TICS pro? Thanks!

Vaison

0 Riley Nguyen 10 months ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

Sorry for the late response as I also experience the same issue where it shows 0 on Num/Den of DPLL. Our team is still looking into the root cause of this in order to update in future software release. In the mean time, if there is any other REF frequency you would like to check, I can help with the DPLL calculation.

I have checked the previous config with 40283203Hz that the device could lock. After loading the config, please try in order: "Write all regs" then "Soft-chip reset" (I noticed you did the opposite order which might cause some registers did not get updated properly).

-Riley

0 Vaison Xia 10 months ago in reply to Riley Nguyen

Prodigy 10 points

Hi, Riley,

Thanks for your help! Your are right. After I followed your order: Write all regs" ,then "Soft-chip reset", I can see DPLL lock after loading your “PRIREF 40283203Hz lock with updated DPLL calculation.tcs” file.

I checked our system design. We also need these 3 clock frequencies below input to LMK05318 PRIREF and SECREF to be locked on DPLL. Would you help provide the tcs file for them? Thanks!

103.759765 MHz

100.708007 MHz

50.354003 MHz

Vaison

0 Riley Nguyen 10 months ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

Good to hear it works for you now. I'll check other input frequencies and get back to you next week.

-Riley

0 Vaison Xia 10 months ago in reply to Riley Nguyen

Prodigy 10 points

Hi, Riley,

I appreciate if you can send me the tcs files this Friday (6/9) for the 3 center clock frequencies I listed. I will take vacation next week and I hope I can complete the debug this week if possible. Thanks!

Best regards,

Vaison

0 Riley Nguyen 10 months ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

Here the configs for the above input frequencies. I have also tested on bench that they are locked to these references.

50354003Hz_REF_Freq.tcs

100708007Hz_REF_Freq.tcs

103759765Hz_REF_Freq.tcs

-Riley

0 Vaison Xia 10 months ago in reply to Riley Nguyen

Prodigy 10 points

Hi, Riley,

Great! Thanks so much for your help! I will test these 3 tcs files on my system.

Vaison

0 Riley Nguyen 10 months ago in reply to Vaison Xia

TI__Intellectual 1435 points

Vaison,

I will close this thread for now. Let me know if you have more questions.

-Riley

0 Vaison Xia 10 months ago in reply to Riley Nguyen

Prodigy 10 points

Hi, Riley,

I tested those 3 tcs files on my system and they all worked to have DPLL locked. Thanks for great help again for this long-time case! You can close this case.

For your TICS Pro software update to fix Num/Den of DPLL showing 0 issue, let me know when your TI team will release a new version software to fix it.

My e-mail is weicheng.xia@intel.com. I appreciate you or someone from your TI team can e-mail to inform me. So that I can update it. Thanks!

Vaison

0 Riley Nguyen 10 months ago in reply to Vaison Xia

TI__Intellectual 1435 points

Hi Vaison,

Glad to hear that! I have forwarded this thread and your email to our team. We will notify you when the new software has this issue fixed. Have a great weekend!

-Riley

Clock & timing

Clock & timing forum

LMK05318: Frequence deviation tolerance for DPLL Primary and Secondary Ref clock Inputs.