LMK04832: Single Loop Phase noise degradation

Hello Deva,

For the simulation, you are using the program for the LMK04832-SP instead of the LMK04832, so make sure to translate your data to the LMK04832 one to make sure nothing changes. Both parts are very similar but still a good thing to check.

Deva Guru said:

2.Is there any better part that could provide less Phase noise degradation at lower offsets(<10KHz) and with 0-delay feature, Sysref generation?

Our RF PLLs and Synchronizers are for this specific purpose! So you can use one of those parts too if that fits your application better. The LMX2572, LMX2594, LMX2595, and the LMX2820 all offer SYSREF and 0-delay mode (they are all automatically single-loop, so no need to worry about that). 

Deva Guru said:

1.Since phase noise is of utmost importance for our application, Kindly confirm if the phase noise degradation will not exceed -4dB degration i.e, -126dBc/Hz @ 100Hz offset when using LMK04832? or will practical implementation incur additional degradation?

I can corroborate this on the bench for you next week if you still prefer the LMK04832 over the other 4 RF products mentioned above. To answer your questions, yes you can expect the -4dB degradation shown in the simulation will not be worse, assuming you have a clean power supply, clean reference (which should be the case with the OCXO), the layout of your board is optimized for best performance, you place the outputs of the LMK04832 to have minimal crosstalk, and it is also dependent in your input signal format. Of course, temperature and voltage supplied will affect the performance of the part, so if within the recommended operations values and not reaching to the absolute maximum ratings you can assume constant performance (with all the previous assumptions are also followed). Hope this helps!

Good luck,

Andrea

Hello Andrea,

Andrea Vallenilla said:

For the simulation, you are using the program for the LMK04832-SP instead of the LMK04832, so make sure to translate your data to the LMK04832 one to make sure nothing changes. Both parts are very similar but still a good thing to check.

Thanks for pointing out, I have changed the device as suggested, also since i need the sysref of all LMK04832 to be phase aligned, I changed the PFD frequency to Sysref frequency(5MHz) to comply with the Zero delay rule(Since LMK04832 has R divider sync, Input need not be GCD(VCO,Sysref), right?)

With the above change, On simulating the Output 100MHz Phase noise in PLLatinum sim software, -4.2dB degradation in phase noise is observed at 100Hz offset as shown below,

1) It would be greatly helpful, if you can share the output 100MHz phase noise data Using LMK04832 with a OSCin Input square wave source of similar phase noise characteristic. Also what is the phase noise degradation of the same when operated in distribution mode(Input : 1600MHz, Output:100MHz)?

2)I went through the post"">e2e.ti.com/.../lmk04828-multi-board-lmk-sync" and i have the below queries,

2.a) Sync event for R divider (caused by SPI or by SYNC/CLKIN0 pin togglig) should meet the setup and hold time of Reference clock Input or VCO cycle?

2.b)As R diver sync is being performed, Sync event for output divider (caused by SPI or by SYNC/CLKIN0 pin togglig) should meet the setup and hold time of Reference clock Input or VCO cycle?

2.c) in case of pulser mode with R divider sync, sysref request should meet the setup and hold time of Reference clock Input or VCO cycle?

2.d)3)"In general, so long as you don't need CLKin0 --> CLKout, or need SYSREF at the same moment using two cascaded devices -- I suggest the LMK04832"
For my configuration, i need Sysref from multiple parallel LMK04832 to be exactly at the same moment <10ps(other than JESD). Can i proceed with LMK04832? also just for information, if i have 2chains of 2nos.cascaded multiple LMK04832 then sysref phase alignment cannot be implemented?

2.e)what is the value of tPDCLKin0_ Propagation Delay from CLKin0 to SDCLKout1 for LMK04832 ?

2.f)generally does zero delay for Input and output clock means determinism between input and output clock phases or Input and output clock phases align at same moment( 0ps propagation delay) ?

3)we have a requirement to phase align sysref and device clock of all LMK04832 <10ps(other than JESD) in multiple power on's. So i intend to do the below,

Align the Pulsor mode 5MHz sysref outputs generated locally by all lmk04832 with OSCin input 100MHz by using R divider sync.

R divider sync,Output divider sync, Sysref request all these shall be generated in phase to 100MHz OSCin input.

Is <10ps phase alignment of sysref possible with above scheme?

Thanks in-advance,

Deva

Hello Deva,

I will get back to you by the end of this week with the phase noise measurements.

All the components mentioned above (output dividers, R dividers, etc), should meet the setup up and hold time of the VCO cycles.

Deva Guru said:

For my configuration, i need Sysref from multiple parallel LMK04832 to be exactly at the same moment <10ps(other than JESD). Can i proceed with LMK04832?

Yes, you just have to make sure to also provide a SYSREF input to the 2nd LMK04832 to ensure all devices are aligned.

Deva Guru said:

? also just for information, if i have 2chains of 2nos.cascaded multiple LMK04832 then sysref phase alignment cannot be implemented?

No, SYSREF alignment should always be able to be implemented from the LMK04832

Deva Guru said:

2.e)what is the value of tPDCLKin0_ Propagation Delay from CLKin0 to SDCLKout1 for LMK04832 ?

This is dependent on frequency, for a 100 MHz output clock it's around 17 VCO cycles. So for SYSREF, it should also be around 17 VCO cycles.

Deva Guru said:

2.f)generally does zero delay for Input and output clock means determinism between input and output clock phases or Input and output clock phases align at same moment( 0ps propagation delay) ?

This first option, 0-delay aligns the input and output phases throughout the life of the clock.

Deva Guru said:

Is <10ps phase alignment of sysref possible with above scheme?

I will get back to you by the end of this week.

Best,

Andrea

Hi Andrea,

Is there any update, awaiting your reply.

Also, what is the  Flicker FOM Normalized to 1 Hz value of PLL2 of LMK04832 ?

Thanks in-advance,

Deva

Hi Deva,

I'll have a look on the above requested data and will respond you by tomorrow.

Thanks!

Regards,

Ajeet Pal

Hi Deva,

Sorry for the delay in response.

Regarding your query on the 100MHz output phase noise degradation @100Hz offset, the LMK04832 has an Norm PLL flicker -128 dBc/Hz @ 10kHz offset (see the note 6 to calculate the phase noise at required output frequency) and at 100MHz output the phase noise will be around -148 dBc/Hz @ 10kHz offset with 10dB/decade slope close to carrier. Hence the device has an close-in noise at 100Hz offset (PLL noise) would be around -128dBc/Hz.

This is the best phase noise, you could get when your reference is at least better than 6-10dB at 100Hz offset.

Deva Guru said:

Also, what is the  Flicker FOM Normalized to 1 Hz value of PLL2 of LMK04832 ?

Normalized flicker at 1Hz will be based on 10dB/decade and it would be around -88dBc/Hz.

Deva Guru said:

Is <10ps phase alignment of sysref possible with above scheme?

The SYSREF alignment between the parts can be possible but the device itself is having CLKout to CLKout skew 60ps. Hence, the phase alignment can vary in this range.

Regarding the multi-device LMK04832 sync, the PLL2 R - divider reset along with ZDM can provide the deterministic phase but it would required to have external SYNC input to reset the PLL2 R divider, which should meet set up and hold timing requirement as well as while reducing the PLL2 phase detector frequency to 5MHz, will degrades the overall phase noise performance (flat noise).

While using the dual PLL nested ZDM, you can have external input frequency same as SYSREF at PLL1 input and can keep the higher VCXO at the PLL2 OSCin input, which will keep device in true ZDM and would improve the overall clock output phase noise performance.

Deva Guru said:

It would be greatly helpful, if you can share the output 100MHz phase noise data Using LMK04832 with a OSCin Input square wave source of similar phase noise characteristic. Also what is the phase noise degradation of the same when operated in distribution mode(Input : 1600MHz, Output:100MHz)?

I'll provide the measured data soon today.

Thanks!

Regards,

Ajeet Pal