Hello,
My customer has an additional question about the following E2E thread.
https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1205337/cdcm7005-sp-vinpp-question/4546540#4546540
The datasheet says that VCXO_IN and VCXO_IN_ are LVPECL inputs.
However, the above E2E thread is mentioning LVCMOS VCXO is also OK.
If 3.3V LVCMOS single-end VCXO is used for VCXO_IN and VCXO_IN_ is biased at 3.3V/2, VINPP voltage could be around 3.3V and it exceeds VINPP(max) 1.5V.
Is this really OK?
Best regards,
K.Hirano