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LMK00105: Differential clock input termination

Part Number: LMK00105
Other Parts Discussed in Thread: CDCM6208,


I have a question as title.
As I read past thread;

There is description about application report (,

but I'm still not clear about differential input termination.

I consider about which circuit attached image below is better AC coupled LVDS with CDCM6208 for 2 types.

Type (1) is 2 AC coupling capacitors and 50 ohm termination for both positive and negative line.

Type (2) is 1 AC coupling capacitor for both positive and negative line and 100 ohm termination across the line.

Mother board is already mounted, and I want to use type (2) to decrease the parts.

I think type(2) will work, but I wonder there is any problem;

As CLKin and CLKin* is pre-biased about 1.4V, something wrong occur because of some difference of pre-biased voltage between CLKin & CLKin*.

If there are no problem, I want use type(2).

Best Regards,


  • Hi Naoyuki,

    Type 1) is recommended in the CDCM6208 datasheet for a situation "without receiver input termination and self biasing" but I am not familiar with Type 2) or how pre-biasing may affect the situation. I have paged a team member more familiar with termination.


    Evan Su

  • Thank you for your reply.
    I hope your team member will bring me further information.

    Best Regards,


  • Hi Naoyuki,

    For Type 2 termination, if the output of CDCM6208 is not Hi-Z or tri stated, then this termination is fine for LMK00105 input. Other wise it would cause chatter when you have a 100 ohm resistor between two inputs in that mode. Because it would overrides the input offset voltage between inputs. 

    DC couple or 100 ohm standard termination before the AC coupling caps would be an option in that case.

    If output of CDCM6208 is always running, then type2 is perfectly fine.



  • Hi Asim,
    Thank you for your reply.

    I understand when CDCM6208 is Hi-Z, the offset voltage  would be overridden and causes chatter.

    As I guessed to use CDCM6208 with Hi-Z mode when PLL is not locked, your further information is very helpful.

    Best regards,