Other Parts Discussed in Thread: LMK1C1103, LMK04832-SP,
Hi team
Could you confirm whether the device can support LVTTL input/output or LVCMOS input/output as default condition?
Regards,
Noriyuki Takahashi
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Hi team
Could you confirm whether the device can support LVTTL input/output or LVCMOS input/output as default condition?
Regards,
Noriyuki Takahashi
Hi Noriyuki,
This device supports LVPECL or LVCMOS inputs.
Regards
Vicente
Vicente,
It seems that the device supports only LVPECL at default condition. The registers need to be changed to support LVCMOS inputs/outputs.
Could you tell any ways to use the devices with LVCOMS inputs/outputs as default condition?
Regards,
Noriyuki Takahashi
Hi Noriyuki,
Device supports SE inputs but the outputs are LVPECL on default, if customer's application requires SE outputs this would have to be changed by user.
Regards,
Vicente
Hi Noriyuki,
Correction: VCXO input pins can support SE inputs, refer to the following thread: https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/1205772/cdcm7005-sp-lvcmos-single-end-vcxo-is-really-used-for-vcxo_in
Common mode voltage and Swing must be taken care of.
Common mode voltage can be taken care of using a resistive divider at each pin where pull up is 82 ohm and pull down is 130 ohm. This will result in VCM = 2 V.
Attach a 0.1uF cap to unused pin with the divider for power filtering.
For the swing, the 50 ohm resistor will be in series with the resistive divider network to produce a Vpp within range.
Regards,
Vicente
Vicente
Please let me confirm again.
If they want to use the device as buffer mode wiht LVCMOS input, they need to add a resistive divider to support LVCMOS input as you mentioned. Is this correct? How about the output? Does the device support LVCMOS output?
If they want to use the device as buffer mode & PLL with LVCMOS input, are there any configuration?
Are there any deivces that can meet requirements below? PLL is want, not must.
1. Input, ouput can support LVTTL or LVCMOS
2. 1:3 buffer
3. Including PLL function
Regards,
Noriyuki Takahashi
Hi Noriyuki,
Outputs can be either SE or LVPECL.
In regards to a 1:3 SE buffer LMK1C1103 would be my first recommendation.
If customer really wants a PLL, CDCS504 is an option but it's an older device with limitations for it's input frequency range:
Regards,
Vicente
Vincentte,
I am looking for -SP grade. Are there any devices?
Regards,
Noriyuki Takahashi
Hi Noriyuki,
CDCM7005-SP or a jitter cleaner like LMK04832-SP would be the only options for native SE inputs/output functionality.