LMK04832: About synchronizing multi-LMK04832 output

In both cases, the answer is yes. But the SYNC is not timing-critical in either case.

When you program LMK04832 channel dividers, the act of programming also triggers a divider reset. Since the SPI clock is much slower than the register reset, the phase of the divider is effectively randomized by the act of programming. So a SYNC is always required to align the dividers on a single device.

However, no SYNC is required to align the SYSREF divider to a repeatable phase offset with respect to the 10MHz input clocks - you can just set the phase detector of PLL1 to 10MHz (i.e. PLL1_R and PLL1_N = 1) to guarantee alignment between the 10MHz input clock edge and the 10MHz SYSREF divider edge. You can then exploit the SYSREF divider phase to re-time the SYNC signal, making the timing of the SYNC signal non-critical. Set the SYNC_DISx bits of each 100MHz output to 0, set the SYSREF_MUX to re-timed SYNC, and toggle SYNC_POL bit to align all phases; reset the SYNC_DISx bits to 1 and restore the SYSREF_MUX to the desired state afterward. Because the SYSREF retimer is aligned with the 10MHz input, and since the 100MHz output is a multiple of 10MHz, the 100MHz clocks will all have a repeatable phase offset with respect to the 10MHz clocks.

If you want, you could design this process to be automatic. By setting SYNC_PLL1_DLD=1 and setting SYNC_MODE to normal sync, you can ensure that a SYNC signal is asserted until PLL1 locks. You would program the device initially with SYSREF_MUX set to retiming mode and the SYNC_DISx bits cleared; the 100MHz outputs would initially be held in a reset state. Then when PLL1 locks, the SYNC condition is lifted synchronously with the SYSREF divider (and therefore the 10MHz input), and the 100MHz outputs are all synchronized. After lock, just set the SYNC_DISx bits back to 1 and set the desired state of the SYSREF_MUX. You may also want to clear SYNC_PLL1_DLD if the pin-based pulser is used, so that loss of lock at PLL1 does not trip the SYSREF pulser by accident. Note loss of lock at PLL1 wouldn't affect the phase relationship of outputs, since they remain in-phase and are divided from the same VCO.

Since the SYSREF is aligned to the 10MHz device, by definition the SYSREF is aligned across different LMKs, so the re-timed SYNC (and subsequently the 100MHz outputs) will also be aligned across different LMKs. Note that loss of lock at PLL1 would temporarily skew different LMKs, but the moment lock is restored on all devices, the same initial phase offset would be restored across all LMKs. In other words, you only ever need to SYNC once, at startup, on each device.

One more thing: you should never need to set SYNC_DISSYSREF=0 with your configuration as described - in other words, the SYSREF divider never needs to be reset. Since SYSREF is in the feedback path, the PLL will ensure a repeatable phase relationship between the 10MHz reference and the SYSREF automatically, independent of the initial SYSREF divider phase.